《计算机体系结构》课程实验31
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2022-08-03
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《计算机体系结构》课程实验指导手册
实验 3：指令流水线仿真程序
背景知识
1. Instruction pipeline
An instruction pipeline is a technique used in the design of computer and other digital electronic
devices to increase their instruction throughput (the number of instructions that can be executed in a
unit of time).
The fundamental idea is to split the processing of a computer instruction into a series of independent
steps, with storage at the end of each step. This allows the computer’s control circuitry to issue
instructions at the processing rate of the slowest step, which is much faster than the time needed to
perform all steps at once. The term pipeline refers to the fact that each step is carrying data at once
(like water), and each step is connected to the next (like the links of a pipe).
Most modern CPUs are driven by a clock. The CPU consists internally of logic and register. When
the clock signal arrives, the flip flops take their new value and the logic then requires a period of
time to decode the new values. Then the next clock pulse arrives and the flip flops again take their
new values, and so on. By breaking the logic into smaller pieces and inserting flip flops between the
pieces of logic, the delay before the logic gives valid outputs is reduced. In this way the clock period
can be reduced. For example, the classic RISC pipeline is broken into five stages with a set of flip
flops between each stage.
1. Instruction fetch
2. Instruction decode and register fetch
3. Execute
4. Memory access
5. Register write back
When a programmer (or compiler) writes assembly code, they make the assumption that each
instruction is executed before execution of the subsequent instruction is begun. This assumption is
invalidated by pipelining. When this causes a program to behave incorrectly, the situation is known
as a hazard. Various techniques for resolving hazards such as forwarding and stalling exist.
A non-pipeline architecture is inefficient because some CPU components (modules) are idle while
another module is active during the instruction cycle. Pipelining does not completely cancel out idle
time in a CPU but making those modules work in parallel improves program execution significantly.
Processors with pipelining are organized inside into stages which can semi-independently work on
separate jobs. Each stage is organized and linked into a ‘chain’ so each stage’s output is fed to
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