9.2.3. Interfaces............................................................................................... 95
9.2.4. Operation............................................................................................... 95
9.3. Parameter...........................................................................................................96
9.4. Configuration Registers.........................................................................................96
9.5. Interface Signals..................................................................................................96
9.6. Ethernet MDIO Core Revision History......................................................................97
10. Intel FPGA 16550 Compatible UART Core....................................................................98
10.1. Core Overview...................................................................................................98
10.2. Feature Description............................................................................................ 98
10.2.1. Unsupported Features.............................................................................99
10.2.2. Interface...............................................................................................99
10.2.3. General Architecture............................................................................. 101
10.2.4. 16550 UART General Programming Flow Chart......................................... 101
10.2.5. Configuration Parameters...................................................................... 103
10.2.6. DMA Support....................................................................................... 103
10.2.7. FPGA Resource Usage........................................................................... 104
10.2.8. Timing and Fmax..................................................................................104
10.2.9. Avalon-MM Agent................................................................................. 105
10.2.10. Over-run/Under-run Conditions............................................................ 106
10.2.11. Hardware Auto Flow-Control.................................................................107
10.2.12. Clock and Baud Rate Selection..............................................................108
10.3. Software Programming Model.............................................................................108
10.3.1. Overview.............................................................................................108
10.3.2. Supported Features.............................................................................. 108
10.3.3. Unsupported Features........................................................................... 109
10.3.4. Configuration....................................................................................... 109
10.3.5. 16550 UART API...................................................................................109
10.3.6. Driver Examples...................................................................................113
10.4. Address Map and Register Descriptions ...............................................................117
10.4.1. rbr_thr_dll...........................................................................................118
10.4.2. ier_dlh................................................................................................ 119
10.4.3. iir.......................................................................................................121
10.4.4. fcr......................................................................................................122
10.4.5. lcr...................................................................................................... 124
10.4.6. mcr.................................................................................................... 126
10.4.7. lsr...................................................................................................... 127
10.4.8. msr.................................................................................................... 129
10.4.9. scr..................................................................................................... 131
10.4.10. afr.................................................................................................... 132
10.4.11. tx_low...............................................................................................133
10.5. Intel FPGA 16550 Compatible UART Core Revision History......................................133
11. UART Core.................................................................................................................135
11.1. Core Overview................................................................................................. 135
11.2. Functional Description.......................................................................................135
11.2.1. Avalon-MM Agent Interface and Registers................................................ 135
11.2.2. RS-232 Interface..................................................................................136
11.2.3. Transmitter Logic..................................................................................136
11.2.4. Receiver Logic......................................................................................136
11.2.5. Baud Rate Generation........................................................................... 137
Contents
Embedded Peripherals IP User Guide
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