STM32 智林开发板例程

/*---------------------------------------------------------------------------- * Name: STM32_Init.c * Purpose: STM32 peripherals initialisation * Version: V1.10 *---------------------------------------------------------------------------- * This file is part of the uVision/ARM development tools. * This software may only be used under the terms of a valid, current, * end user licence from KEIL for a compatible version of KEIL software * development tools. Nothing else gives you the right to use this software. * * Copyright (c) 2005-2007 Keil Software. All rights reserved. *----------------------------------------------------------------------------*/ #include <stm32f10x_lib.h> // STM32F10x Library Definitions #include "STM32_Reg.h" // missing bit definitions //-------- <<< Use Configuration Wizard in Context Menu >>> ----------------- // //=========================================================================== Clock Configuration // <e0> Clock Configuration // <h> Clock Control Register Configuration (RCC_CR) // <e1.24> PLLON: PLL enable // <i> Default: PLL Disabled // <o2.18..21> PLLMUL: PLL Multiplication Factor // <i> Default: PLLSRC * 2 // <0=> PLLSRC * 2 // <1=> PLLSRC * 3 // <2=> PLLSRC * 4 // <3=> PLLSRC * 5 // <4=> PLLSRC * 6 // <5=> PLLSRC * 7 // <6=> PLLSRC * 8 // <7=> PLLSRC * 9 // <8=> PLLSRC * 10 // <9=> PLLSRC * 11 // <10=> PLLSRC * 12 // <11=> PLLSRC * 13 // <12=> PLLSRC * 14 // <13=> PLLSRC * 15 // <14=> PLLSRC * 16 // <o2.17> PLLXTPRE: HSE divider for PLL entry // <i> Default: HSE // <0=> HSE // <1=> HSE / 2 // <o2.16> PLLSRC: PLL entry clock source // <i> Default: HSI/2 // <0=> HSI / 2 // <1=> HSE (PLLXTPRE output) // </e> // <o1.19> CSSON: Clock Security System enable // <i> Default: Clock detector OFF // <o1.18> HSEBYP: External High Speed clock Bypass // <i> Default: HSE oscillator not bypassed // <o1.16> HSEON: External High Speed clock enable // <i> Default: HSE oscillator OFF // <o1.3..7> HSITRIM: Internal High Speed clock trimming <0-31> // <i> Default: 0 // <o1.0> HSION: Internal High Speed clock enable // <i> Default: internal 8MHz RC oscillator OFF // </h> // <h> Clock Configuration Register Configuration (RCC_CFGR) // <o2.24..26> MCO: Microcontroller Clock Output // <i> Default: MCO = noClock // <0=> MCO = noClock // <4=> MCO = SYSCLK // <5=> MCO = HSI // <6=> MCO = HSE // <7=> MCO = PLLCLK / 2 // <o2.22> USBPRE: USB prescaler // <i> Default: USBCLK = PLLCLK / 1.5 // <0=> USBCLK = PLLCLK / 1.5 // <1=> USBCLK = PLLCLK // <o2.14..15> ADCPRE: ADC prescaler // <i> Default: ADCCLK=PCLK2 / 2 // <0=> ADCCLK = PCLK2 / 2 // <1=> ADCCLK = PCLK2 / 4 // <2=> ADCCLK = PCLK2 / 6 // <3=> ADCCLK = PCLK2 / 8 // <o2.11..13> PPRE2: APB High speed prescaler (APB2) // <i> Default: PCLK2 = HCLK // <0=> PCLK2 = HCLK // <4=> PCLK2 = HCLK / 2 // <5=> PCLK2 = HCLK / 4 // <6=> PCLK2 = HCLK / 8 // <7=> PCLK2 = HCLK / 16 // <o2.8..10> PPRE1: APB Low speed prescaler (APB1) // <i> Default: PCLK1 = HCLK // <0=> PCLK1 = HCLK // <4=> PCLK1 = HCLK / 2 // <5=> PCLK1 = HCLK / 4 // <6=> PCLK1 = HCLK / 8 // <7=> PCLK1 = HCLK / 16 // <o2.4..7> HPRE: AHB prescaler // <i> Default: HCLK = SYSCLK // <0=> HCLK = SYSCLK // <8=> HCLK = SYSCLK / 2 // <9=> HCLK = SYSCLK / 4 // <10=> HCLK = SYSCLK / 8 // <11=> HCLK = SYSCLK / 16 // <12=> HCLK = SYSCLK / 64 // <13=> HCLK = SYSCLK / 128 // <14=> HCLK = SYSCLK / 256 // <15=> HCLK = SYSCLK / 512 // <o2.0..1> SW: System Clock Switch // <i> Default: SYSCLK = HSE // <0=> SYSCLK = HSI // <1=> SYSCLK = HSE // <2=> SYSCLK = PLLCLK // </h> // <o3>HSE: External High Speed Clock [Hz] <4000000-16000000> // <i> clock value for the used External High Speed Clock (4MHz <= HSE <= 16MHz). // <i> Default: 8000000 (8MHz) // </e> End of Clock Configuration #define __CLOCK_SETUP 1 #define __RCC_CR_VAL 0x01010082 #define __RCC_CFGR_VAL 0x00118402 #define __HSE 12000000 //=========================================================================== Independent Watchdog Configuration // <e0> Independent Watchdog Configuration // <o1> IWDG period [us] <125-32000000:125> // <i> Set the timer period for Independent Watchdog. // <i> Default: 1000000 (1s) // </e> #define __IWDG_SETUP 0 #define __IWDG_PERIOD 0x001E8480 //=========================================================================== System Timer Configuration // <e0> System Timer Configuration // <o1.2> System Timer clock source selection // <i> Default: SYSTICKCLK = HCLK/8 // <0=> SYSTICKCLK = HCLK/8 // <1=> SYSTICKCLK = HCLK // <o2> SYSTICK period [ms] <1-1000:10> // <i> Set the timer period for System Timer. // <i> Default: 1 (1ms) // <o1.1> System Timer interrupt enabled // </e> #define __SYSTICK_SETUP 0 #define __SYSTICK_CTRL_VAL 0x00000006 #define __SYSTICK_PERIOD 0x000000C8 //=========================================================================== Real Time Clock Configuration // <e0> Real Time Clock Configuration // <o1.8..9> RTC clock source selection // <i> Default: No Clock // <0=> No Clock // <1=> RTCCLK = LSE (32,768kHz) // <2=> RTCCLK = LSI (32 kHz) // <3=> RTCCLK = HSE/128 // <o2> RTC period [ms] <10-1000:10> // <i> Set the timer period for Real Time Clock. // <i> Default: 1000 (1s) // <h> RTC Time Value // <o3> Hour <0-23> // <o4> Minute <0-59> // <o5> Second <0-59> // </h> // <h> RTC Alarm Value // <o6> Hour <0-23> // <o7> Minute <0-59> // <o8> Second <0-59> // </h> // <e9> RTC interrupts // <o10.0> RTC_CRH.SECIE: Second interrupt enabled // <o10.1> RTC_CRH.ALRIE: Alarm interrupt enabled // <o10.2> RTC_CRH.OWIE: Overflow interrupt enabled // </e> // </e> #define __RTC_SETUP 0 #define __RTC_CLKSRC_VAL 0x00000100 #define __RTC_PERIOD 0x000003E8 #define __RTC_TIME_H 0x00 #define __RTC_TIME_M 0x00 #define __RTC_TIME_S 0x00 #define __RTC_ALARM_H 0x00 #define __RTC_ALARM_M 0x01 #define __RTC_ALARM_S 0x00 #define __RTC_INTERRUPTS 0x00000001 #define __RTC_CRH 0x00000001 //=========================================================================== Timer Configuration // <e0> Timer Configuration //------