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### MIPS32 架构详解 #### 一、MIPS32 架构概述 MIPS32架构是MIPS Technologies公司开发的一种精简指令集计算（RISC）架构，适用于广泛的处理器设计，包括高性能服务器、嵌入式系统和个人计算机等。MIPS32架构在设计上具有高效性、灵活性和可扩展性的特点，使其成为学习和研究计算机体系结构的绝佳选择。 #### 二、MIPS32架构特点 1. **精简指令集**：MIPS32采用RISC设计理念，指令集简洁明了，大多数指令只需一个时钟周期即可完成执行。 2. **寄存器窗口技术**：为了提高函数调用效率，MIPS32使用了寄存器窗口技术，减少了函数调用时对内存的访问需求。 3. **可扩展性**：MIPS32支持多种扩展指令集，如浮点运算单元FPU等，可以根据不同应用场景进行定制。 4. **统一的数据路径**：所有整数和浮点运算使用相同的数据路径，简化了硬件设计。 5. **内存一致性模型**：MIPS32定义了严格的内存一致性模型，确保多处理器系统中的数据一致性。 6. **分支预测**：通过动态预测分支方向，减少流水线停顿，提高性能。 7. **支持多种操作系统**：MIPS32可以运行各种操作系统，如Linux、FreeBSD等。 #### 三、MIPS32指令集 MIPS32的指令集包括了算术逻辑指令、控制转移指令、数据传输指令以及特殊用途指令。其中，典型的指令有： - **算术逻辑指令**：例如ADD（加法）、SUB（减法）、AND（逻辑与）、OR（逻辑或）等。 - **控制转移指令**：如J（跳转）、BEQ（相等时跳转）、BNE（不等时跳转）等。 - **数据传输指令**：例如LW（加载字）、SW（存储字）等用于数据读写的指令。 - **特殊用途指令**：例如MTC0/MFC0（向/从控制寄存器传输数据）等。 #### 四、MIPS32架构下的编程实践 1. **汇编语言编程**：使用MIPS汇编语言可以直接控制底层硬件资源，实现对MIPS32处理器的高效利用。 2. **高级语言编程**：通过GCC等编译器将C/C++等高级语言转换为MIPS32汇编代码，便于编写复杂的软件程序。 3. **调试工具**：使用诸如MARS等模拟器进行程序调试，帮助理解MIPS32架构的工作原理。 4. **性能优化**：通过循环展开、数据局部性优化等技术提高程序执行效率。 #### 五、MIPS32架构的学习资源 1. **官方文档**：MIPS Technologies提供的官方文档是最权威的学习资源，其中包括了大量的技术细节和示例。 2. **在线课程**：Coursera、edX等在线平台提供了关于MIPS架构的课程，适合初学者入门。 3. **书籍教材**：《Computer Organization and Design》（David A. Patterson & John L. Hennessy著）是一本经典的参考书，涵盖了MIPS架构的各个方面。 #### 六、总结 MIPS32架构是一种广泛应用于教育和工业领域的RISC架构，以其简单而强大的设计著称。学习MIPS32不仅可以帮助理解现代处理器的设计理念，还能为开发高性能应用奠定基础。通过深入研究MIPS32的指令集和编程实践，可以进一步掌握计算机系统的底层工作原理，对于从事计算机科学及相关领域的专业人士来说，这是一份宝贵的知识财富。

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Document Number: MD00082

Revision 2.50

July 1, 2005

MIPS Technologies, Inc.

1225 Charleston Road

Mountain View, CA 94043-1353

MIPS32® Architecture For Programmers

Volume I: Introduction to the MIPS32®

Architecture

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MIPS32® Architecture For Programmers Volume I, Revision 2.50

Template: B1.14, Built with tags: 2B ARCH MIPS32

MIPS32® Architecture For Programmers Volume I, Revision 2.50 i

Table of Contents

Chapter 1 About This Book ................................................................................................................................................. 1

1.1 Typographical Conventions ................................................................................................................................... 1

1.1.1 Italic Text ..................................................................................................................................................... 1

1.1.2 Bold Text ..................................................................................................................................................... 1

1.1.3 Courier Text ................................................................................................................................................. 1

1.2 UNPREDICTABLE and UNDEFINED ................................................................................................................ 2

1.2.1 UNPREDICTABLE ..................................................................................................................................... 2

1.2.2 UNDEFINED ............................................................................................................................................... 2

1.2.3 UNSTABLE ................................................................................................................................................. 2

1.3 Special Symbols in Pseudocode Notation .............................................................................................................. 3

1.4 For More Information ............................................................................................................................................ 5

Chapter 2 The MIPS Architecture: An Introduction ............................................................................................................ 7

2.1 MIPS32 and MIPS64 Overview ............................................................................................................................ 7

2.1.1 Historical Perspective .................................................................................................................................. 7

2.1.2 Architectural Evolution ................................................................................................................................ 7

2.1.3 Architectural Changes Relative to the MIPS I through MIPS V Architectures .......................................... 9

2.2 Compliance and Subsetting .................................................................................................................................... 9

2.3 Components of the MIPS Architecture ................................................................................................................ 10

2.3.1 MIPS Instruction Set Architecture (ISA) ................................................................................................... 10

2.3.2 MIPS Privileged Resource Architecture (PRA) ........................................................................................ 10

2.3.3 MIPS Application Specific Extensions (ASEs) ......................................................................................... 10

2.3.4 MIPS User Defined Instructions (UDIs) .................................................................................................... 11

2.4 Architecture Versus Implementation ................................................................................................................... 11

2.5 Relationship between the MIPS32 and MIPS64 Architectures ........................................................................... 11

2.6 Instructions, Sorted by ISA .................................................................................................................................. 12

2.6.1 List of MIPS32 Instructions ....................................................................................................................... 12

2.6.2 List of MIPS64 Instructions ....................................................................................................................... 13

2.7 Pipeline Architecture ............................................................................................................................................ 13

2.7.1 Pipeline Stages and Execution Rates ......................................................................................................... 13

2.7.2 Parallel Pipeline ......................................................................................................................................... 14

2.7.3 Superpipeline ............................................................................................................................................. 14

2.7.4 Superscalar Pipeline ................................................................................................................................... 14

2.8 Load/Store Architecture ....................................................................................................................................... 15

2.9 Programming Model ............................................................................................................................................ 15

2.9.1 CPU Data Formats ..................................................................................................................................... 16

2.9.2 FPU Data Formats ...................................................................................................................................... 16

2.9.3 Coprocessors (CP0-CP3) ........................................................................................................................... 16

2.9.4 CPU Registers ............................................................................................................................................ 16

2.9.5 FPU Registers ............................................................................................................................................ 18

2.9.6 Byte Ordering and Endianness .................................................................................................................. 21

2.9.7 Memory Access Types ............................................................................................................................... 25

2.9.8 Implementation-Specific Access Types ..................................................................................................... 26

2.9.9 Cache Coherence Algorithms and Access Types ...................................................................................... 26

2.9.10 Mixing Access Types ............................................................................................................................... 26

Chapter 3 Application Specific Extensions ........................................................................................................................ 27

3.1 Description of ASEs ............................................................................................................................................. 27

3.2 List of Application Specific Instructions ............................................................................................................. 28

3.2.1 The MIPS16e™ Application Specific Extension to the MIPS32Architecture .......................................... 28

3.2.2 The MDMX™ Application Specific Extension to the MIPS64 Architecture ........................................... 28

ii MIPS32® Architecture For Programmers Volume I, Revision 2.50

3.2.3 The MIPS-3D® Application Specific Extension to the MIPS32 Architecture ......................................... 28

3.2.4 The SmartMIPS® Application Specific Extension to the MIPS32 Architecture ...................................... 28

3.2.5 The MIPS® DSP Application Specific Extension to the MIPS32 Architecture ....................................... 28

3.2.6 The MIPS® MT Application Specific Extension to the MIPS32 Architecture ......................................... 29

Chapter 4 Overview of the CPU Instruction Set ................................................................................................................ 31

4.1 CPU Instructions, Grouped By Function ............................................................................................................. 31

4.1.1 CPU Load and Store Instructions .............................................................................................................. 31

4.1.2 Computational Instructions ........................................................................................................................ 34

4.1.3 Jump and Branch Instructions .................................................................................................................... 37

4.1.4 Miscellaneous Instructions ......................................................................................................................... 39

4.1.5 Coprocessor Instructions ............................................................................................................................ 42

4.2 CPU Instruction Formats ..................................................................................................................................... 43

Chapter 5 Overview of the FPU Instruction Set ................................................................................................................ 45

5.1 Binary Compatibility ............................................................................................................................................ 45

5.2 Enabling the Floating Point Coprocessor ............................................................................................................. 46

5.3 IEEE Standard 754 ............................................................................................................................................... 46

5.4 FPU Data Types ................................................................................................................................................... 46

5.4.1 Floating Point Formats ............................................................................................................................... 46

5.4.2 Fixed Point Formats ................................................................................................................................... 50

5.5 Floating Point Register Types .............................................................................................................................. 50

5.5.1 FPU Register Models ................................................................................................................................. 51

5.5.2 Binary Data Transfers (32-Bit and 64-Bit) ................................................................................................ 51

5.5.3 FPRs and Formatted Operand Layout ........................................................................................................ 52

5.6 Floating Point Control Registers (FCRs) ............................................................................................................. 52

5.6.1 Floating Point Implementation Register (FIR, CP1 Control Register 0) ................................................... 53

5.6.2 Floating Point Control and Status Register (FCSR, CP1 Control Register 31) ......................................... 55

5.6.3 Floating Point Condition Codes Register (FCCR, CP1 Control Register 25) ........................................... 57

5.6.4 Floating Point Exceptions Register (FEXR, CP1 Control Register 26) .................................................... 58

5.6.5 Floating Point Enables Register (FENR, CP1 Control Register 28) ......................................................... 58

5.7 Formats of Values Used in FP Registers ............................................................................................................. 59

5.8 FPU Exceptions .................................................................................................................................................... 60

5.8.1 Exception Conditions ................................................................................................................................. 61

5.9 FPU Instructions .................................................................................................................................................. 64

5.9.1 Data Transfer Instructions .......................................................................................................................... 64

5.9.2 Arithmetic Instructions .............................................................................................................................. 65

5.9.3 Conversion Instructions ............................................................................................................................. 67

5.9.4 Formatted Operand-Value Move Instructions ........................................................................................... 68

5.9.5 Conditional Branch Instructions ................................................................................................................ 69

5.9.6 Miscellaneous Instructions ......................................................................................................................... 70

5.10 Valid Operands for FPU Instructions ................................................................................................................. 70

5.11 FPU Instruction Formats .................................................................................................................................... 72

5.11.1 Implementation Note ............................................................................................................................... 73

Appendix A Instruction Bit Encodings .............................................................................................................................. 77

A.1 Instruction Encodings and Instruction Classes .................................................................................................... 77

A.2 Instruction Bit Encoding Tables ........................................................................................................................... 77

A.3 Floating Point Unit Instruction Format Encodings .............................................................................................. 84

Appendix B Revision History ............................................................................................................................................ 87

MIPS32® Architecture For Programmers Volume I, Revision 2.50 iii

List of Figures

Figure 2-1: Relationship between the MIPS32 and MIPS64 Architectures...................................................................... 11

Figure 2-2: One-Deep Single-Completion Instruction Pipeline........................................................................................ 13

Figure 2-3: Four-Deep Single-Completion Pipeline ......................................................................................................... 14

Figure 2-4: Four-Deep Superpipeline................................................................................................................................ 14

Figure 2-5: Four-Way Superscalar Pipeline...................................................................................................................... 15

Figure 2-6: CPU Registers................................................................................................................................................. 18

Figure 2-7: FPU Registers for a 32-bit FPU...................................................................................................................... 20

Figure 2-8: FPU Registers for a 64-bit FPU if Status

is 1............................................................................................. 21

Figure 2-9: FPU Registers for a 64-bit FPU if Status

is 0............................................................................................. 22

Figure 2-10: Big-Endian Byte Ordering............................................................................................................................ 23

Figure 2-11: Little-Endian Byte Ordering......................................................................................................................... 23

Figure 2-12: Big-Endian Data in Doubleword Format...................................................................................................... 24

Figure 2-13: Little-Endian Data in Doubleword Format................................................................................................... 24

Figure 2-14: Big-Endian Misaligned Word Addressing ................................................................................................... 25

Figure 2-15: Little-Endian Misaligned Word Addressing................................................................................................. 25

Figure 3-1: MIPS ISAs and ASEs..................................................................................................................................... 27

Figure 3-2: User-Mode MIPS ISAs and Optional ASEs................................................................................................... 27

Figure 4-1: Immediate (I-Type) CPU Instruction Format................................................................................................. 44

Figure 4-2: Jump (J-Type) CPU Instruction Format ......................................................................................................... 44

Figure 4-3: Register (R-Type) CPU Instruction Format ................................................................................................... 44

Figure 5-1: Single-Precisions Floating Point Format (S).................................................................................................. 47

Figure 5-2: Double-Precisions Floating Point Format (D)................................................................................................ 47

Figure 5-3: Paired Single Floating Point Format (PS) ...................................................................................................... 48

Figure 5-4: Word Fixed Point Format (W)........................................................................................................................ 50

Figure 5-5: Longword Fixed Point Format (L) ................................................................................................................. 50

Figure 5-6: FPU Word Load and Move-to Operations ..................................................................................................... 51

Figure 5-7: FPU Doubleword Load and Move-to Operations........................................................................................... 52

Figure 5-8: Single Floating Point or Word Fixed Point Operand in an FPR .................................................................... 52

Figure 5-9: Double Floating Point or Longword Fixed Point Operand in an FPR ........................................................... 52

Figure 5-10: Paired-Single Floating Point Operand in an FPR......................................................................................... 52

Figure 5-11: FIR Register Format ..................................................................................................................................... 53

Figure 5-12: FCSR Register Format.................................................................................................................................. 55

Figure 5-13: FCCR Register Format................................................................................................................................. 57

Figure 5-14: FEXR Register Format ................................................................................................................................. 58

Figure 5-15: FENR Register Format ................................................................................................................................. 58

Figure 5-16: Effect of FPU Operations on the Format of Values Held in FPRs............................................................... 60

Figure 5-17: I-Type (Immediate) FPU Instruction Format ............................................................................................... 73

Figure 5-18: R-Type (Register) FPU Instruction Format.................................................................................................. 73

Figure 5-19: Register-Immediate FPU Instruction Format ............................................................................................... 73

Figure 5-20: Condition Code, Immediate FPU Instruction Format .................................................................................. 73

Figure 5-21: Formatted FPU Compare Instruction Format............................................................................................... 73

Figure 5-22: FP RegisterMove, Conditional Instruction Format ...................................................................................... 73

Figure 5-23: Four-Register Formatted Arithmetic FPU Instruction Format..................................................................... 74

Figure 5-24: Register Index FPU Instruction Format........................................................................................................ 74

Figure 5-25: Register Index Hint FPU Instruction Format ............................................................................................... 74

Figure 5-26: Condition Code, Register Integer FPU Instruction Format.......................................................................... 74

Figure A-1: Sample Bit Encoding Table........................................................................................................................... 78