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6.2.4 Interrupt Preemption ............................................................................................ 203
6.2.5 ARM A8 INTC Spurious Interrupt Handling ................................................................. 203
6.3 ARM Cortex-A8 Interrupts .............................................................................................. 204
6.4 ARM Cortex-M3 Interrupts .............................................................................................. 208
6.5 PWM Events .............................................................................................................. 210
6.6 Interrupt Controller Registers ........................................................................................... 211
6.6.1 INTC Registers .................................................................................................. 211
7 Memory Subsystem ......................................................................................................... 386
7.1 GPMC ..................................................................................................................... 387
7.1.1 Introduction ...................................................................................................... 387
7.1.2 Integration ........................................................................................................ 390
7.1.3 Functional Description .......................................................................................... 392
7.1.4 Use Cases ....................................................................................................... 491
7.1.5 Registers ......................................................................................................... 502
7.2 OCMC-RAM .............................................................................................................. 535
7.2.1 Introduction ...................................................................................................... 535
7.2.2 Integration ........................................................................................................ 536
7.3 EMIF ....................................................................................................................... 537
7.3.1 Introduction ...................................................................................................... 537
7.3.2 Integration ........................................................................................................ 539
7.3.3 Functional Description .......................................................................................... 541
7.3.4 Use Cases ....................................................................................................... 559
7.3.5 EMIF4D Registers .............................................................................................. 559
7.3.6 DDR2/3/mDDR PHY Registers ............................................................................... 600
7.4 ELM ........................................................................................................................ 609
7.4.1 Introduction ...................................................................................................... 609
7.4.2 Integration ........................................................................................................ 610
7.4.3 Functional Description .......................................................................................... 611
7.4.4 Basic Programming Model ..................................................................................... 614
7.4.5 ELM Registers ................................................................................................... 620
8 Power, Reset, and Clock Management (PRCM) .................................................................... 632
8.1 Power, Reset, and Clock Management ............................................................................... 633
8.1.1 Introduction ...................................................................................................... 633
8.1.2 Device Power-Management Architecture Building Blocks ................................................. 633
8.1.3 Clock Management ............................................................................................. 633
8.1.4 Power Management ............................................................................................ 639
8.1.5 PRCM Module Overview ....................................................................................... 647
8.1.6 Clock Generation and Management .......................................................................... 648
8.1.7 Reset Management ............................................................................................. 664
8.1.8 Power-Up/Down Sequence .................................................................................... 673
8.1.9 IO State ........................................................................................................... 673
8.1.10 Voltage and Power Domains ................................................................................. 673
8.1.11 Device Modules and Power Management Attributes List ................................................. 674
8.1.12 Clock Module Registers ....................................................................................... 677
8.1.13 Power Management Registers ............................................................................... 834
9 Control Module ................................................................................................................ 875
9.1 Introduction ............................................................................................................... 876
9.2 Functional Description ................................................................................................... 876
9.2.1 Control Module Initialization ................................................................................... 876
9.2.2 Pad Control Registers .......................................................................................... 876
9.2.3 EDMA Event Multiplexing ...................................................................................... 877
9.2.4 Device Control and Status ..................................................................................... 878
9.2.5 DDR PHY ........................................................................................................ 885
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SPRUH73F–October 2011–Revised June 2012 Contents
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