基于TDC的全数字锁相环研究与设计.docx资源-CSDN文库

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摘要

随着集成电路的飞速发展，锁相环已经成为现代时钟电路的重要组成部分，是现代超大

规模集成电路中必不可少的核心组成部件，用它来产生和提供片内高速时钟。本文在大量阅

读国内外相关锁相环技术的文献基础上，介绍了锁相环技术的发展概况、基本概念、分类及

应用，深入分析研究了全数字锁相环的结构原理，并设计了一种基于时间数字转换器的全数

字锁相环（ADPLL）。

本文给出了全数字锁相环的系统结构及各个子模块的电路，建立了全数字锁相环的数学

模型，并分析了它的稳定性和可行性。本文针对传统时间数字转换电路的不足，通过加入上

升沿检测电路，扩大计数器位宽，使之不仅能完成时数转换的基本功能，而且提高了时数转

换的准确性，扩大了相位差的测量范围；采用一个环形振荡器同时给数控振荡器和时间数字

转换器提供多相参考时钟信号，它的转换精度乘积为 1，使环路对工艺、电压、温度都不敏

感，增强了稳定性；通过加入可编程任意整数分频器进行分频，使得反馈时钟波形占空比保

持为 50%；通过简化传统数控振荡器的结构，使之基本功能保持不变，且有效地减小了电路

的占用面积。此外，还介绍了各个数字模块的设计实现和编码技巧、数字集成电路的开发设

计流程以及数模混合仿真流程。

本文基于标准 0.18µm CMOS 的数字逻辑工艺，采用自顶向下的设计方法完成了整个全

数字锁相环的 RTL 级设计、仿真以及关键模块的版图实现。仿真结果表明，锁相环的锁定输

出频率范围为 64MHz~640MHz，分频系数范围为 27~70。当参考频率为 10MHz 时，环路锁

定时间在 12μs 以内。

关键词:

全数字锁相环，鉴相器，时间数字转换器，数控振荡器，数字分频器

Abstract

With the rapid development of integrated circuits, a PLL (Phase-Locked Loop) has played an

important role in VLSI circuits as an important part of modern clock generation circuits, which is

used to provide on-chip high-speed clocks.Based on reading a large number of domestic and foreign

literature on phase-locked loop technologies, we firstly introduce the development, concept,

classification and application of PLL, and deeply analyse the structural principle of All-Digital PLL.

Then the ADPLL (All-Digital PLL) with TDC (Time to Digital Converter) is designed in this paper.

In this paper, the ADPLL’s system structure, sub-circuit blocks, and mathematical model are

proposed, and its stability and viability are analyzed. Among them, the traditional TDC is improved

by adding the circuit of rising edge detection and expanding the width of counter, which not only

achieves the basic function, but also improves the accuracy and the measurement range of the TDC.

A FRO’s (Free-running Ring Oscillator) outputs offer a multi-phase reference signal for the DCO

(Digital-Controlled Oscillator) and TDC, so the product of convention resolution is fixed to 1. It not

only makes the system more stable and reliable, but also be insensitive to the number of modules to

process, voltage and temperature. Adding the programmable arbitrary integer divider, the feedback

clock's waveform duty cycle is fifty percent. Simplifying the structure of the traditional DCO, the

basic functions remain unchanged, and the circuit area is effectively reduced. Furthermore, this

paper focuses on introducing the design method and programming skills of all of digital circuits, the

digital integrated circuit design flow and mixed analog-digital simulation process.

Based on standard 0.18μm CMOS technology, the proposed ADPLL’s RTL-level modeling,

simulation and the key module’s layout are implemented using the top-down design method.

Simulation results show that the output frequency range from 64 MHz to 640 MHz, the frequency

multiplication factor range from 27 to 70. When the reference frequency is 10MHz, the loop

locking time is within 12μs.

Key words: All-Digital PLL，Phase Detector（PD），Time to Digital Converter（TDC），

Digital-Controlled Oscillator（DCO），Digital Divider

第一章绪论 ...............................................................................................................................................................1

1.1 课题的研究背景及意义 ..............................................................................................................................1

1.1.1 锁相环的发展概况 ...........................................................................................................................1

1.1.2 全数字锁相环研究的意义 ...............................................................................................................2

1.2 国内外的研究现状 ......................................................................................................................................3

1.3 论文的结构 ..................................................................................................................................................5

第二章锁相环简介 ...................................................................................................................................................6

2.1 锁相环的组成及原理 ...................................................................................................................................6

2.1.1 鉴相器 ...............................................................................................................................................6

2.1.2 环路滤波器 .......................................................................................................................................7

2.1.3 压控振荡器 .......................................................................................................................................9

2.2 锁相环的分类及应用 ................................................................................................................................10

2.3 锁相环的主要性能参数 ............................................................................................................................12

2.4 本章小结 ....................................................................................................................................................12

第三章数字锁相环的结构 .....................................................................................................................................14

3.1 数字锁相环的分类 ....................................................................................................................................14

3.2 全数字锁相环的组成 ................................................................................................................................15

3.2.1 数字鉴相器 .....................................................................................................................................15

3.2.2 时间数字转换器 .............................................................................................................................17

3.2.3 数字滤波器 .....................................................................................................................................19

3.2.4 数控振荡器 .....................................................................................................................................21

3.2.5 数字分频器 .....................................................................................................................................24

3.2.6 环形振荡器 .....................................................................................................................................25

3.3 全数字锁相环的数学分析 ........................................................................................................................26

3.3.1 鉴相器的数学模型 .........................................................................................................................27

3.3.2 数字滤波器的数学模型 .................................................................................................................28

3.3.3 数控振荡器的数学模型 .................................................................................................................28

3.3.4 数字分频器的数学模型 .................................................................................................................28

3.3.5 锁相环的数学模型 .........................................................................................................................29

3.4 本章小结 ....................................................................................................................................................31

第四章基于 TDC 的全数字锁相环设计 ...............................................................................................................32

4.1

Verilog HDL 的介绍 ...................................................................................................................................32

4.2 锁相环各个模块的设计 ............................................................................................................................33

4.2.1 鉴相器的设计 .................................................................................................................................33

4.2.2 TDC 的设计 .....................................................................................................................................35

4.2.3 DCO 的设计.....................................................................................................................................39

4.2.4 数字分频器的设计 .........................................................................................................................41

4.2.5 FRO 的设计 .....................................................................................................................................43

4.3 全数字锁相环的仿真 ................................................................................................................................44

4.3.1 数模混合仿真流程 .........................................................................................................................44

4.3.2 仿真分析 .........................................................................................................................................45

4.4 本章小结 ....................................................................................................................................................47

第五章锁相环关键模块的后端设计 .....................................................................................................................48

5.1 数字 ASIC 的设计流程 .............................................................................................................................48

III

5.2 TDC 的后端设计 ........................................................................................................................................50

5.2.1 TDC 逻辑综合 .................................................................................................................................50