Addendum List for Revision 7.1
MPC5607B Reference Manual Errata, Rev. 1
Freescale Semiconductor2
1 Addendum List for Revision 7.1
Table 1. MPC5607BRM Rev 7.1 Addenda
Location Description
Chapter 1, Preface, page 22 In Table 1-1, Guide to this reference manual, Line 12 WKUP, change the description to read:
Always-active analog block. Details configuration of 2 internal (API/RTC) and 27 external (pin)
low power mode wakeup sources.
Chapter 1, Preface, page 23 In Table 1 (Guide to this reference manual), Line 17, eDMA Channel Multiplexer (DMA_MUX),
change the description to read:
“Operation and configuration information for the eDMA multiplexer, which takes the 59
possible eDMA sources (triggers from the DSPI, eMIOS, I
2
C, ADC and LINFlexD) and
multiplexes them onto the 16 eDMA channels.” (59 sources, 16 channels)
Chapter 1, Preface, page 27 In Section 1.6.1, The MPC5607B document set, remove bullet item
“e200z4 Power Architecture Core Reference Manual.”
Chapter 1, Preface, page 27 In Section 1.6.1, The MPC5607B document set, change bullet item “Configuring CPU memory,
branch and cache optimizations” to “Configuring CPU memory and branch optimizations.”
Chapter 1, Preface, page 30 In Section 1.7.3, Software design, remove the paragraph “The MMU translates physical memory
addresses for use by the CPU and it must be configured before any peripherals or memories
are available for use by the CPU. See the e200z4 Power Architecture Core Reference Manual
for details on how to configure the MMU.”
Chapter 6, Clock Description,
page 132
Add Note: to Section 6.8.4.1, Crystal clock monitor:
Note: Functional FXOSC monitoring can only be guaranteed when the FXOSC frequency is
greater than (FIRC / 2
RCDIV
)+0.5MHz.
Add Note: to Section 6.8.4.2, FMPLL clock monitor:
Note: Functional FMPLL monitoring can only be guaranteed when the FMPLL frequency is
greater than (FIRC / 4) + 0.5 MHz.
Chapter 9, Reset Generation
Module (MC_RGM), page
232
Replaced Section 9.4.7, Boot Mode Capturing, with the following:
The MC_RGM samples PA[9:8] whenever RESET is asserted until five FIRC (16 MHz internal
RC oscillator) clock cycles before its deassertion edge. The result of the sampling is used at
the beginning of reset PHASE3 for boot mode selection and is retained after RESET has been
deasserted for subsequent boots after reset sequences during which RESET is not asserted.
Note: In order to ensure that the boot mode is correctly captured, the application needs to
apply the valid boot mode value the entire time that RESET is asserted.
RESET can be asserted as a consequence of the internal reset generation. This will force
re-sampling of the boot mode pins. (See Table 9-12 for details.)
Chapter 13, Real Time Clock /
Autonomous Periodic
Interrupt (RTC/API), page 270
In Table 13-3 (RTCC field descriptions), update the Note in the RTCC[APIVAL] field description:
Note: API functionality starts only when APIVAL is nonzero. The first API interrupt takes two
more cycles because of synchronization of APIVAL to the RTC clock, and APIVAL + 1 cycles
for subsequent occurrences. After that, interrupts are periodic in nature. Because of
synchronization issues, the minimum supported value of APIVAL is 4.
