2048点FFT算法verilog代码.doc

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// Interface:

//

// Synchronization:

// clock_c : Clock input.

// enable_i : Synchronous enable.

// reset_i : Synchronous reset.

//

// sync_o : Output sync pulse occurs one frame before data output.

// data_0_o : Output data 0. Width is 2 * precision. Real on the left, imag on the right.

// data_1_o : Output data 1. Width is 2 * precision. Real on the left, imag on the right.

//

// Built In Parameters:

//

// FFT Points = 2048

// Precision = 18

//

//

// Interface

//

// Build Name : cf_fft_2048_18

// Clock Domains : clock_c

// Vector Input : enable_i(1)

// Vector Input : reset_i(1)

// Vector Input : sync_i(1)

// Vector Input : data_0_i(36)

// Vector Input : data_1_i(36)

// Vector Output : sync_o(1)

`timescale 1 ns / 1 ns

module cf_fft_2048_18 (clock_c, enable_i, reset_i, sync_i, data_0_i, data_1_i, sync_o, data_0_o,

data_1_o);

input clock_c;

input enable_i;

output [35:0] data_1_o;

wire n1;

wire [35:0] n2;

wire [35:0] n3;

cf_fft_2048_18_1 s1 (clock_c, sync_i, data_0_i, data_1_i, enable_i, reset_i, n1, n2, n3);

assign sync_o = n1;

assign data_0_o = n2;

assign data_1_o = n3;

endmodule

input i5;

output o1;

output [35:0] o2;

output [35:0] o3;

wire s1_1;

wire [35:0] s1_2;

wire [35:0] s1_3;

wire s2_1;

wire [35:0] s2_2;

wire [35:0] s2_3;

wire [35:0] s4_3;

wire s5_1;

wire [35:0] s5_2;

wire [35:0] s5_3;

cf_fft_2048_18_25 s1 (clock_c, s3_1, s3_2, s3_3, i4, i5, s1_1, s1_2, s1_3);

cf_fft_2048_18_8 s2 (clock_c, s1_1, s1_2, s1_3, i4, i5, s2_1, s2_2, s2_3);

cf_fft_2048_18_6 s3 (clock_c, s4_1, s4_2, s4_3, i4, i5, s3_1, s3_2, s3_3);

module cf_fft_2048_18_2 (clock_c, i1, i2, i3, i4, i5, o1, o2, o3);

input clock_c;

input i1;

input [35:0] i2;

input [35:0] i3;

input i4;

input i5;

output o1;

output [35:0] o2;

wire [1:0] n6;

wire [35:0] n7;

wire [35:0] n8;

wire [35:0] n9;

wire [35:0] n10;

wire [35:0] n11;

wire [35:0] n12;

wire s13_1;

wire [71:0] s14_1;

wire s15_1;

assign n2 = s16_1[9];

assign n3 = ~n2;

assign n4 = {s16_1[8],

s16_1[7],

s16_1[6],

s16_1[5],

s16_1[4],

n4[2],

n4[3],

n4[4],

n4[5],

n4[6],

n4[7],

n4[8]};

assign n6 = {s15_2, s15_1};

assign n7 = {s15_3[71],

s15_3[70],

s15_3[63],

s15_3[62],

s15_3[61],

s15_3[60],

s15_3[59],

s15_3[58],

s15_3[57],

s15_3[56],

s15_3[55],

s15_3[54],

s15_3[48],

s15_3[47],

s15_3[46],

s15_3[45],

s15_3[44],

s15_3[43],

s15_3[42],

assign n8 = {s15_3[35],

s15_3[34],

s15_3[33],

s15_3[32],

s15_3[31],

s15_3[30],

s15_3[29],

s15_3[28],

s15_3[27],

s15_3[26],

s15_3[19],

s15_3[18],

s15_3[17],

s15_3[16],

s15_3[15],

s15_3[14],

s15_3[13],

s15_3[12],

s15_3[11],

s15_3[10],