24C04.pdfeepromdatasheet资源-CSDN文库

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### 24C04 EEPROM 数据手册解析 #### 概述本文档旨在解析与解释“24C04.pdf eeprom datasheet”的关键信息，该文档提供了ST24C04、ST25C04、ST24W04、ST25W04等系列4Kbit串行I2C总线EEPROM产品的详细规格和技术信息。这些EEPROM（电可擦可编程只读存储器）产品具有用户自定义块写保护功能，并且支持高达一百万次擦写周期以及四十年的数据保留时间。 #### 主要特性 1. **擦写周期与数据保留**: 提供一百万次擦写周期的能力，确保了产品的耐用性；同时，长达四十年的数据保留时间使得存储的数据在长时间内保持稳定。 2. **供电电压范围**: - ST24x04版本：3V至5.5V - ST25x04版本：2.5V至5.5V 3. **硬件写保护版本**: - ST24W04和ST25W04 4. **接口兼容性**: 支持全兼容的I2C总线标准，采用双向数据总线和串行时钟进行通信。 5. **写入操作模式**: - 字节写入 (最多4字节) - 页面写入 (最多8字节) 6. **读取操作模式**: - 字节读取 - 随机读取 - 连续读取 7. **自定时编程周期**: 内置自定时机制，简化编程过程。 8. **地址自动递增**: 在连续写入或读取操作期间，自动更新内存地址，提高效率。 9. **增强型ESD/闩锁性能**: 改善静电放电和闩锁效应的耐受能力。 #### 功能描述 - **产品系列**: 本规范涵盖了ST24/25C04和ST24/25W04系列4Kbit I2C总线EEPROM产品。其中，“C”代表标准版，“W”代表硬件写控制版本。 - **存储容量**: 4Kbit，组织为两个256x8位的区块。 - **制造工艺**: 采用STMicroelectronics的Hi-Endurance Advanced CMOS技术，保证了产品的高耐久性和长数据保留时间。 - **封装类型**: 提供塑料双列直插式封装(Plastic Dual-in-Line)和塑料小外形封装(Plastic Small Outline)两种选择。 #### 接口引脚 - **E1、E2**: 芯片使能输入端，用于选择特定设备。 - **SDA**: 串行数据地址输入/输出端，用于双向数据传输。 - **SCL**: 串行时钟输入端，提供时钟信号以同步数据传输。 - **MODE/WC**: 对于标准版，该引脚用于多字节/页面写入模式；对于硬件写控制版本，该引脚用于写控制。 - **VCC**: 电源电压输入端。 - **VSS**: 地线端。 - **PRE**: 写保护启用端，仅适用于ST24/25W04产品。 #### 应用场景 - **消费电子**: 如智能手机、平板电脑中的配置存储。 - **工业控制**: 存储校准数据、配置参数等。 - **汽车电子**: 保存诊断数据、配置设置等。 - **网络设备**: 存储固件升级信息、网络配置参数等。 #### 总结 ST24/25x04系列EEPROM以其出色的耐久性、广泛的供电电压范围、灵活的读写模式及与I2C总线的完全兼容性，在多种应用场景中表现出色。通过其独特的设计，如自定义块写保护、自定时编程周期等特性，使得这些器件成为各种电子产品中的理想选择。

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ST24C04, ST25C04

ST24W04, ST25W04

4 Kbit Serial I

C Bus EEPROM

with User-Defined Block Write Protection

February 1999 1/16

AI00851E

E1-E2 SDA

ST24x04

ST25x04

MODE/WC*

SCL

PRE

Figure 1. Logic Diagram

1 MILLION ERASE/WRITE CYCLES with

40 YEARS DATA RETENTION

SINGLE SUPPLY VOLTAGE:

– 3V to 5.5V for ST24x04 versions

– 2.5V to 5.5V for ST25x04 versions

HARDWARE WRITE CONTROL VERSIONS:

ST24W04 and ST25W04

PROGRAMMABLE WRITE PROTECTION

TWO WIRE SERIAL INTERFACE, FULLY I

BUS COMPATIBLE

BYTE and MULTIBYTE WRITE (up to 4

BYTES)

PAGE WRITE (up to 8 BYTES)

BYTE, RANDOM and SEQUENTIAL READ

MODES

SELF TIMED PROGRAMMING CYCLE

AUTOMATIC ADDRESS INCREMENTING

ENHANCED ESD/LATCH UP

PERFORMANCES

DESCRIPTION

This specification covers a range of 4 Kbits I

C bus

EEPROM products, the ST24/25C04 and the

ST24/25W04. In the text, products are referred to

as ST24/25x04, where "x" is: "C" for Standard

version and "W" for hardware Write Control ver-

sion.

PRE Write Protect Enable

E1-E2 Chip Enable Inputs

SDA Serial Data Address Input/Output

SCL Serial Clock

MODE

Multibyte/Page Write Mode

(C version)

WC Write Control (W version)

Supply Voltage

Ground

Table 1. Signal Names

SO8 (M)

150mil Width

PSDIP8 (B)

0.25mm Frame

Note:

WC signal is only available for ST24/25W04 products.

The ST24/25x04 are 4 Kbit electrically erasable

programmable memories (EEPROM), organized

as 2 blocks of 256 x8 bits. They are manufactured

in STMicroelectronics’s Hi-Endurance Advanced

CMOS technology which guarantees an endur-

ance of one million erase/write cycles with a data

retention of 40 years.

Both Plastic Dual-in-Line and Plastic Small Outline

packages are available.

The memories are compatible with the I

C stand-

ard, two wire serial interface which uses a bi-direc-

tional data bus and serial clock. The memories

carry a built-in 4 bit, unique device identification

code (1010) corresponding to the I

C bus defini-

tion. This is used together with 2 chip enable inputs

(E2, E1) so that up to 4 x 4K devices may be

attached to the I

C bus and selected individually.

The memories behave as a slave device in the I

protocol with all memory operations synchronized

by the serial clock. Read and write operations are

initiated by a START condition generated by the

bus master. The START condition is followed by a

stream of 7 bits (identification code 1010), plus one

read/write bit and terminated by an acknowledge

bit.

SDAV

SCL

MODE/WCE1

PRE V

AI00852E

ST24x04

ST25x04

Figure 2A. DIP Pin Connections

AI01107E

SDAV

SCL

MODE/WCE1

PRE V

ST24x04

ST25x04

Figure 2B. SO Pin Connections

DESCRIPTION (cont’d)

Symbol Parameter Value Unit

Ambient Operating Temperature –40 to 125

STG

Storage Temperature –65 to 150

LEAD

Lead Temperature, Soldering (SO8 package)

(PSDIP8 package)

40 sec

10 sec

215

260

Input or Output Voltages –0.6 to 6.5 V

Supply Voltage –0.3 to 6.5 V

ESD

Electrostatic Discharge Voltage (Human Body model)

(2)

4000 V

Electrostatic Discharge Voltage (Machine model)

(3)

500 V

Notes:

1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings"

may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other

conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum

Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other

relevant quality documents.

2. MIL-STD-883C, 3015.7 (100pF, 1500

Ω

3. EIAJ IC-121 (Condition C) (200pF, 0

Ω

Table 2. Absolute Maximum Ratings

(1)

2/16

ST24/25C04, ST24/25W04

Mode RW bit MODE Bytes Initial Sequence

Current Address Read ’1’ X 1 START, Device Select, R

W = ’1’

Random Address Read

’0’

START, Device Select, R

W = ’0’, Address,

’1’ reSTART, Device Select, R

W = ’1’

Sequential Read ’1’ X 1 to 512 Similar to Current or Random Mode

Byte Write ’0’ X 1 START, Device Select, R

W = ’0’

Multibyte Write

(2)

’0’ V

4 START, Device Select, RW = ’0’

Page Write ’0’ V

8 START, Device Select, RW = ’0’

Notes:

1. X = V

or V

2. Multibyte Write not available in ST24/25W04 versions.

Table 4. Operating Modes

(1)

Device Code Chip Enable

Block

Select

Bit b7 b6 b5 b4 b3 b2 b1 b0

Device Select 1 0 1 0 E2 E1 A8 R

Note:

The MSB b7 is sent first.

Table 3. Device Select Code

When writing data to the memory it responds to the

8 bits received by asserting an acknowledge bit

during the 9th bit time. When data is read by the

bus master, it acknowledges the receipt of the data

bytes in the same way. Data transfers are termi-

nated with a STOP condition.

Power On Reset: V

lock out write protect. In

order to prevent data corruption and inadvertent

write operations during power up, a Power On

Reset (POR) circuit is implemented. Until the V

voltage has reached the POR threshold value, the

internal reset is active, all operations are disabled

and the device will not respond to any command.

In the same way, when V

drops down from the

operating voltage to below the POR threshold

value, all operations are disabled and the device

will not respond to any command. A stable V

must be applied before applying any logic signal.

SIGNAL DESCRIPTIONS

Serial Clock (SCL). The SCL input pin is used to

synchronize all data in and out of the memory. A

resistor can be connected from the SCL line to V

to act as a pull up (see Figure 3).

Serial Data (SDA). The SDA pin is bi-directional

and is used to transfer data in or out of the memory.

It is an open drain output that may be wire-OR’ed

with other open drain or open collector signals on

the bus. A resistor must be connected from the SDA

bus line to V

to act as pull up (see Figure 3).

Chip Enable (E1 - E2). These chip enable inputs

are used to set the 2 least significant bits (b2, b3)

of the 7 bit device select code. These inputs may

be driven dynamically or tied to V

or V

establish the device select code.

Protect Enable (PRE). The PRE input pin, in ad-

dition to the status of the Block Address Pointer bit

(b2, location 1FFh as in Figure 7), sets the PRE

write protection active.

Mode (MODE). The MODE input is available on pin

7 (see also

WC feature) and may be driven dynami-

cally. It must be at V

or V

for the Byte Write

mode, V

for Multibyte Write mode or V

for Page

Write mode. When unconnected, the MODE input

is internally read as V

(Multibyte Write mode).

Write Control (

WC). An hardware Write Control

feature (

WC) is offered only for ST24W04 and

ST25W04 versions on pin 7. This feature is usefull

to protect the contents of the memory from any

erroneous erase/write cycle. The Write Control sig-

nal is used to enable (

WC = V

) or disable (WC =

) the internal write protection. When uncon-

nected, the

WC input is internally read as V

and

the memory area is not write protected.

3/16

ST24/25C04, ST24/25W04

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guoyuyu_

2014-04-25

usefull datasheet for my research

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