DE1-SoC Guide
05/09/2016 Page | 2
7.3.3.1 System Manager ....................................................................................................................... 19
7.3.3.2 FPGA Manager ......................................................................................................................... 19
7.3.4 Interface Peripherals .................................................................................................................... 20
7.3.4.1 GPIO Interfaces ......................................................................................................................... 20
7.3.5 On-Chip Memory .......................................................................................................................... 20
7.3.5.1 On-Chip RAM ............................................................................................................................ 20
7.3.5.2 Boot ROM ................................................................................................................................. 20
7.4 HPS-FPGA Interfaces ............................................................................................................................ 20
7.5 HPS Address Map ................................................................................................................................. 20
7.5.1 HPS Address Spaces ..................................................................................................................... 20
7.5.2 HPS Peripheral Region Address Map ............................................................................................ 22
7.6 HPS Boong and FPGA Configuraon .................................................................................................. 24
7.6.1 HPS Boot and FPGA Configuraon Ordering ................................................................................ 24
7.6.2 Zooming In On the HPS Boot Process ........................................................................................... 26
7.6.2.1 Preloader .................................................................................................................................. 27
8 Using the Cyclone V – General Information ................................................................................................. 28
8.1 Introduction ......................................................................................................................................... 28
8.2 FPGA-only ............................................................................................................................................. 28
8.3 HPS & FPGA .......................................................................................................................................... 28
8.3.1 Bare-metal Application ................................................................................................................ 28
8.3.2 Application Over an Operating System (Linux) ............................................................................ 29
8.4 Goals ..................................................................................................................................................... 29
8.5 Project Structure .................................................................................................................................. 29
9 Using the Cyclone V – Hardware .................................................................................................................. 31
9.1 General Quartus Prime Setup .............................................................................................................. 31
9.2 System Design with Qsys – Nios II ........................................................................................................ 31
9.3 System Design with Qsys – HPS ........................................................................................................... 34
9.3.1 Instantiating the HPS Component ................................................................................................ 34
9.3.1.1 FPGA Interfaces Tab ................................................................................................................. 34
9.3.1.2 Peripheral Pins Tab ................................................................................................................... 35
9.3.1.2.1 Theory ................................................................................................................................ 35
9.3.1.2.2 Configuration ..................................................................................................................... 36
9.3.1.3 HPS Clocks Tab ......................................................................................................................... 38
9.3.1.4 SDRAM Tab ............................................................................................................................... 38