SoC-FPGA-Design-Guide-master.zip
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2019-12-31
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SoC-FPGA-Design-Guide-master.zip （215个子文件） 
alt_clock_manager.c 201KB alt_clock_manager.c 201KB alt_generalpurpose_io.c 35KB alt_generalpurpose_io.c 35KB alt_generalpurpose_io.c 35KB alt_generalpurpose_io.c 35KB alt_globaltmr.c 26KB alt_globaltmr.c 26KB hps_linux.c 5KB hps_linux.c 5KB hps_baremetal.c 3KB hps_baremetal.c 3KB nios.c 800B nios.c 795B
SoC-FPGA Design Guide [DE1-SoC Edition].docx 12.35MB SoC-FPGA Design Guide [DE0-Nano-SoC Edition].docx 10.89MB debug_setup.ds 1KB debug_setup.ds 1KB HPS Block Diagram.emf 779KB HPS Block Diagram.emf 779KB Altera SoC FPGA Device.emf 280KB Altera SoC FPGA Device.emf 280KB Independent FPGA Configuration and HPS Booting.emf 183KB Independent FPGA Configuration and HPS Booting.emf 183KB HPS Address Space Relations.emf 166KB HPS Address Space Relations.emf 166KB FPGA Configuration before HPS Boot.emf 134KB FPGA Configuration before HPS Boot.emf 134KB HPS Boot before FPGA Configuration.emf 131KB HPS Boot before FPGA Configuration.emf 131KB Project Folder Structure.emf 118KB Project Folder Structure.emf 118KB HPS Boot Flows.emf 72KB HPS Boot Flows.emf 72KB HPS Boot Flow until Preloader.emf 21KB HPS Boot Flow until Preloader.emf 21KB
LAP logo.gif 2KB LAP logo.gif 2KB .gitignore 143B .gitignore 143B .gitignore 19B .gitignore 19B .gitignore 9B .gitignore 9B .gitignore 8B .gitignore 8B .gitignore 8B .gitignore 8B hps_linux.h 2KB hps_linux.h 2KB hps_baremetal.h 2KB hps_baremetal.h 2KB hps_soc_system.h 1KB hps_soc_system.h 1KB
DE1-SoC Connection Photo.jpg 2.28MB DE0-Nano-SoC Connection Photo.jpg 1.99MB DE0-Nano-SoC Front.jpg 199KB DE1-SoC Front.jpg 191KB DE0-Nano-SoC Back.jpg 178KB Block diagram of the DE1-SoC.jpg 150KB Block diagram of the DE0-Nano-SoC.jpg 137KB Terasic DE0-Nano-SoC Board.jpg 110KB Terasic DE1-SoC Board.jpg 104KB EPFL logo.jpg 55KB EPFL logo.jpg 55KB LICENSE 1KB
DDR3 SDRAM Datasheet.pdf 2.81MB DDR3 SDRAM Datasheet.pdf 2.81MB SoC-FPGA Design Guide [DE1-SoC Edition].pdf 4.32MB SoC-FPGA Design Guide.pdf 4.16MB SoC-FPGA Design Guide [DE0-Nano-SoC Edition].pdf 4.1MB DE1-SoC Schematic.pdf 1.98MB DE0-Nano-SoC Schematic.pdf 1.49MB SDRAM Datasheet.pdf 1.3MB
DE1-SoC Back.png 1.17MB Registers View (All + GPIO1 + HEX0).png 184KB Registers View (All + GPIO1 + HEX0).png 184KB FPGA_peripherals_connected_to_hps.png 151KB New debug configuration dialog connection tab.png 143KB New debug configuration dialog connection tab.png 143KB Qsys_with_initial_hps.png 135KB New debug configuration dialog connection tab.png 133KB New debug configuration dialog connection tab.png 133KB New debug configuration dialog debugger tab.png 132KB New debug configuration dialog debugger tab.png 132KB New debug configuration dialog debugger tab.png 131KB New debug configuration dialog debugger tab.png 131KB FPGA_peripherals_connected_to_hps.png 130KB Basic_NiosII_with_SDRAM_and_JTAG_UART_and_LEDs.png 118KB Qsys_with_initial_hps.png 114KB Basic_NiosII_with_SDRAM_and_JTAG_UART.png 102KB HPS_KEY and HPS_LED Schematic.png 98KB Basic_NiosII_with_onchip_memory_and_JTAG_UART_and_LEDs.png 98KB Target Selection.png 98KB New debug configuration dialog files tab.png 93KB New debug configuration dialog files tab.png 93KB Qsys_peripheral_pins_GPIO_exported.png 91KB Qsys_peripheral_pins_GPIO_exported.png 91KB HPS_KEY and HPS_LED Schematic.png 88KB Basic_NiosII_with_onchip_memory_and_JTAG_UART.png 83KB共 215 条
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