1
High Performance PDM Stereo Audio ADC
FEATURES
• High performance advanced delta-
sigma audio ADC
• Dynamic range: 95 dB @ 0 dB PGA, 91
dB @ 23 dB PGA, 86 dB @ 32 dB PGA
• -88 dB THD+N
• Low noise PGA
• 8 to 96 kHz sampling frequency
• Low power
APPLICATIONS
• Mic Array
• Soundbar
• Audio Interface
• Digital TV
• A/V Receiver
• DVR
• NVR
ORDERING INFORMATION
ES7202 -40°C ~ +85°C
QFN-16
BLOCK DIAGRAM
ES7202
AINLP/AINLN
AINRP/AINRN
PGA
PDM
Data
Interface
Advanced
Delta-sigma
Modulator
Clock Manager
Reset
I
2
C
Interface
DATA
CLOCK
RESETb
CCLK CDATA AD0 AD1 AD2
Everest Semiconductor Confidential ES7202
Revision 3.0 2 October 2020
Latest datasheet: www.everest-semi.com
1. PIN OUT AND DESCRIPTION ................................................................................................ 4
2. TYPICAL APPLICATION CIRCUIT .......................................................................................... 5
3. MICRO-CONTROLLER CONFIGURATION INTERFACE ...................................................... 5
4. ELECTRICAL CHARACTERISTICS ....................................................................................... 7
ABSOLUTE MAXIMUM RATINGS .................................................................................................. 7
RECOMMENDED OPERATING CONDITIONS ................................................................................ 7
ADC ANALOG AND FILTER CHARACTERISTICS AND SPECIFICATIONS .......................................... 7
DC CHARACTERISTICS .................................................................................................................. 7
I
2
C SWITCHING SPECIFICATIONS (SLOW SPEED MODE/HIGH SPEED MODE) ............................. 8
PDM DATA SWITCHING SPECIFICATIONS .................................................................................... 8
5. CONFIGURATION REGISTER DEFINITION .......................................................................... 9
REGISTER 0X00 –RESET CONTROL, DEFAULT 00010000 ............................................................. 9
REGISTER 0X01 – MODE CONTROL, DEFAULT 00000000 ............................................................ 9
REGISTER 0X02 – CLOCK DIVIDE, DEFAULT 00000100 ................................................................ 9
REGISTER 0X03 – CLOCK OFF, DEFAULT 00000000 ..................................................................... 9
REGISTER 0X04 – TIME CONTROL 1 FOR VMID CHARGE, DEFAULT 00000001 ........................... 9
REGISTER 0X05 – TIME CONTROL 2 FOR VMID CHARGE, DEFAULT 00011000 ......................... 10
REGISTER 0X06 – CHIP STATUS, DEFAULT 00000000 ................................................................ 10
REGISTER 0X07 – PDM INTERFACE CONTRL, DEFAULT 00110000 ............................................ 10
REGISTER 0X08 –MISC CONTROL, DEFAULT 00000010 ............................................................. 10
REGISTER 0X10 – ANALOG SYSTEM, DEFAULT 11111111 ......................................................... 11
REGISTER 0X11 – ANALOG SYSTEM, DEFAULT 00001100 ......................................................... 11
REGISTER 0X12 – ANALOG SYSTEM, DEFAULT 01010101 ......................................................... 11
REGISTER 0X13 – ANALOG SYSTEM, DEFAULT 01010101 ......................................................... 12
REGISTER 0X14 – ANALOG SYSTEM, DEFAULT 10001100 ......................................................... 13
REGISTER 0X15 – ANALOG SYSTEM, DEFAULT 00110011 ......................................................... 13
REGISTER 0X16 – ANALOG SYSTEM, DEFAULT 00110011 ......................................................... 14
REGISTER 0X17 – ANALOG SYSTEM, DEFAULT 00110011 ......................................................... 15
REGISTER 0X18 – ANALOG SYSTEM, DEFAULT 01000100 ......................................................... 16
REGISTER 0X19 – ANALOG SYSTEM, DEFAULT 00000000 ......................................................... 16
REGISTER 0X1A – ANALOG SYSTEM, DEFAULT 00000000 ......................................................... 17
REGISTER 0X1B – ANALOG SYSTEM, DEFAULT 00000000 ......................................................... 17
REGISTER 0X1C – ANALOG SYSTEM, DEFAULT 11111000 ......................................................... 17
REGISTER 0X1D – ANALOG SYSTEM, DEFAULT 00011000 ......................................................... 18
Everest Semiconductor Confidential ES7202
Revision 3.0 3 October 2020
Latest datasheet: www.everest-semi.com
REGISTER 0X1E – ANALOG SYSTEM, DEFAULT 00011000 ......................................................... 18
REGISTER 0XFD – DEVICE ID1, DEFAULT 01110010 ................................................................... 18
REGISTER 0XFE – DEVICE ID0, DEFAULT 00000001 ................................................................... 18
6. PACKAGE .............................................................................................................................. 20
7. CORPORATE INFORMATION .............................................................................................. 21
8. IMPORTANT NOTICE AND DISCLAIMER ............................................................................ 21
Everest Semiconductor Confidential ES7202
Revision 3.0 4 October 2020
Latest datasheet: www.everest-semi.com
1. PIN OUT AND DESCRIPTION
Pin Name
Pin number
Input or Output
Pin Description
CCLK, CDATA
16, 15
I/O
I
2
C clock and data
AD0, AD1, AD2
4, 5, 6
I
I
2
C addresses
CLOCK, DATA 3, 2 I, O PDM clock and data
RESETb
1
I
Active low reset
AINLP, AINLN
AINRP, AINRN
14, 13
7, 8
I
I
Analog left inputs
Analog right inputs
VDD, GND 11, 10 I Power supply
REFP
9
O
Filtering capacitor connection
REFQ
12
O
Filtering capacitor connection
ES7202
AINLN
AINLP
CDATA
CCLK
13
14
15
16
RESETb
DATA
CLOCK
AD0
1
2
3
4
REFQ
VDD
GND
REFP
12
11
10
9
8
7
6
5
AINRN
AINRP
AD2
AD1
Everest Semiconductor Confidential ES7202
Revision 3.0 5 October 2020
Latest datasheet: www.everest-semi.com
2. TYPICAL APPLICATION CIRCUIT
3. MICRO-CONTROLLER CONFIGURATION INTERFACE
The device supports standard I
2
C micro-controller configuration interface. External micro-
controller can completely configure the device through writing to internal configuration
registers.
I
2
C interface is a bi-directional serial bus that uses a serial data line (CDATA) and a serial clock
line (CCLK) for data transfer. The timing diagram for data transfer of this interface is given in
Figure 1a and Figure 1b. Data are transmitted synchronously to CCLK clock on the CDATA line on
a byte-by-byte basis. Each bit in a byte is sampled during CCLK high with MSB bit being
transmitted firstly. Each transferred byte is followed by an acknowledge bit from receiver to pull
the CDATA low. The transfer rate of this interface can be up to 400 kbps.
A master controller initiates the transmission by sending a “start” signal, which is defined as a
high-to-low transition at CDATA while CCLK is high. The first byte transferred is the slave address.
It is a seven-bit chip address followed by a RW bit. The chip address must be 0110 x, where x
equals AD2 AD1 AD0. The RW bit indicates the slave data transfer direction. Once an
U5
VCC
GND
OUT+
OUT-
U6
VCC
GND
OUT+
OUT-
1uF
1uF
1uF
1uF
AGND
AGND
VDD_M IC
MEMS
MEMS
4.7uF or 10uF capacitor is for better audio performance.
The filter capacitors on REFP and REFQ pins must be located as close to ES7202 package as possible.
MIC
MIC
0 0 0
I2C CHIP ADDRESSAD2 AD1 AD0
0 0 1
0x30 (7bit) / 0x60 (8bit)
0x31 (7bit) / 0x62 (8bit)
0 1 1
0x32 (7bit) / 0x64 (8bit)0 1 0
0x33 (7bit) / 0x66 (8bit)
1 0 0
0x35 (7bit) / 0x6a (8bit)1 0 1
0x34 (7bit) / 0x68 (8bit)
1 1 1
1 1 0 0x36 (7bit) / 0x6c (8bit)
0x37 (7bit) / 0x6e (8bit)
33pF
AGND
One 33pF capacitor is
recommended for PDM_CLK
U4
ES 7202
RESETb
1
DATA
2
CLO CK
3
AD0
4
AD1
5
AD2
6
AINRP
7
AINRN
8
REFP
9
GND
10
VDD
11
REFQ
12
AI NLN
13
AI NLP
14
CDATA
15
CCLK
16
PAD
17
10K
1uF
AGND
VDD ( 1. 8V TO 3. 3V )
PDM_CLK
PDM_DATA
10K / NC
NC/10K
VDD ( 1. 8V TO 3. 3V )
AGND
10K / NC
NC/10K
10K / NC
NC/10K
I2C SDA
I2C SCL
2K
2K
VDD ( 1. 8V TO 3. 3V )
1uF
1uF
AGND
AGND
1uF
AGND
VDD ( 1. 8V TO 3. 3V )
