Using VMM RAL to verify resiter/memory

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使用VMM RAL进行Register 、memory、验证
Table of figures Figurc 1. RaL implementation in a VMM cnvironment Figure2. Building a ral aware environment…… 垂音垂看D 看垂看 Figure 3. Scripts required in RAL integration 899 Figure 4. Transactor class for writes/reads 10 Figure 5. Example of registers and a memory spec Figure6. Main ral file…… ·.·.··::·:···:·.··· Figure 7. RaL file for register with contiguous fields Figure 8. RAL file for register with non contiguous fields 234568 Figure9. ral generated file for a standard memory as register array………………,16 Figure 10 task from class Figure 1l Generated classes for registers and memories 20 Figure 12. External user defined constraint defined in external file..............21 Figure13. Automatic dut initialization.,…,,…,,…, …21 Figure 14. Reset test using RAL.....23 Figure 15. Field write access type test using Figure 16. Coverage model using ral............. ..·....··· 26 Figure 17. Example of coverage results for a limited number of ral variables. ........................27 Figurc 18. RTL representation of a register with contiguous ficlo :.·:·.:·.:·.:·;···· 28 Figure 19. RTL representation of a register with non-contiguous fields 28 Figure 20 Backdoor Read/Write tasks created by ralgen script 30 Figure 21. Custom backdoor implementation for a memory modeled as register array ..........32 Figure 22. Memory entry backdoor registration process 33 Figure 23. Access randomization method …34 SNUG San josc 2008 A Fully reusable register/Memory Access Solution: USing VMM RAL Introduction Most of today' s modern designs have hundreds if not thousands of registers and lots of on chip memory Continuously increasing number of registers in a design makes register/memory verification a growing challenge for verification engineers writing manual register/memory test cases and test environments. Moreover, changing specs during the cycle of a design may result in unnecessary churn in documentation, verification environment and/or register/memory test cases In turn, this significantly impacts the productivity, and increases the probability of introducing human errors in the process. Hence the need for a streamlined methodology and a tool which ties the spec to the verification environment and makes register/memory testing an automatic process. VMM Register Abstraction Layer (RaL) from Synopsys is a tool that addresses the above concerns and it was used in conducting register/memory test in an existing VMM environment.A fixed sequence of events and commands was defined in order to create the methodology around raL 1. 1. RAL-Description and main Features VMM RAL is a vmm application package which helps create an object oriented abstraction layer to model registers and memories from a dut. a ral model is created from fields which are grouped in registers. Register and memories are grouped into blocks which are static entities with their own registers and memories and sometimes with their own verification Blocks may be further grouped in systems. Thus, RaL is trying to mimic exact design hierarchy and naming of different design entities. For each element in a RaL model- field, register, block or system, there is a class which abstracts the read and write accesses to that element Users are encouraged to read [l for more details about ral structure. Also, an interesting paper B3 on RVM ral has been published and the user may be interested to read it in order to have a complete picture of VMM RAL. It is not the goal of this paper to go into details previousl published on Ral RAL has a number of features which help in dUt verification for complex designs that contain a large number of registers and/or memories. Some of them are presented below. However, a more comprehensive list is can be found in [1, 2, 3] abstract physical location of the registers and the fields. -The user is not required to know the exact address of a register in the memory map or the exact position of a field a register. The user has to know only the name of the register or field which are already part of the spec. RaL will identify the correct address and field position in the register based on the name provided by the user SNUG San josc 2008 4 A Fully reusable register/Memory Access Solution: USing VMM RAL Flexibility and transparency in switching from frontdoor to backdoor accesses This feature provides the user with a valuable tool for dut initialization or an alternative to time consuming frontdoor accesses after complete equivalency between frontdoor and backdoor has been separately proven this feature also has the potential to expose incorrect bus connections insidc the dut or bctwcen the dut and verification environment. Potential issues may be triggered when using frontdoor and backdoor accesses in an alternative fashion for a specific access at a random address The content of registers is mirrored in an external data structure -the ral abstraction model maintains a mirror with what it thinks it is the most up to date value of the registers inside the DUT. Register values can be accessed in zero time after a frontdoor access or dut can be updated with the values from the mirror ral is also able to skip some updates of the dut if the same value is required to be loaded into DUT from the mirror when using particular RAL commands which are specified later in this scction. Thc advantagc of this fcaturc is thc saving of unnecessary clock cyclcs usually wasted with updating the register or memory location with same value when this is not really intended. Resetting the abstraction model sets the mirror to the resets value specified in the spec Independence of tests and register specifications -Register fields can be moved between physical registers without changing the test It is recommended to have differer names for fields in a block. This is particularly useful when a register is moved from one block to another or when fields are reshuffled in within a register during project development The test should not be affected by changes in the spec since it is independent of the cxact location of the register in the memory map or the ficld in the register During the projcct dcvclopmcnt somc other RAL fcaturcs wcrc found uscful in building an automatic testbench Predefined register types- The user has the option to use some of the predefined register types as: ro(read only), rw(read/write), wlc(write I to clear), wo(write only), rc(read to clear) and much more, all described in detail in [1] Access taskS.- These are methods of accessing either dut or ral mirror Some of the tasks proven to be most useful in this project are listed below. However, for a complete list refer to [1. Moreover, 3 shows a partial list of access tasks which are among the most used ones 2 This task gives the user the register value from the DUT. The reglster's mirror in RaL is automatically updated following the read task. This access automatically creates a read command on the physical bus into the dUt This task writes the data provided by the user into the register inside DUT. The registers mirror in ral is automatically updated following the write The task automatically creates a write command on the physical bus into the DUT SNUG San josc 2008 5 A Fully reusable register/Memory Access Solution: USing VMM RAL This task updates the values from the Ral mirror into the register inside the dut. It can be applied at block level in which case it automatically updates all registers from that block or system level in which case it updates all blocks from the system. The command skips updating the registers from the dut which have no mirror changes. This saves clock cycles for registers with no mirror update from the reset value This task updates Ral mirror with the value of the register from nside dUt. It can be used to automatically check if the value retrieved from DUT compared correctly with the value from the mirror. This command will always perform a dUt physical access since ral doesnt know what value will be read from the DUt. It exists at block level and if called it runs thru all registers from a block and updates their mirror accordingly. This task can also be called from system levcl in which casc it loops thru all the blocks in a systcm This task provides the value from ral mirror (it can be done at register or field level). It does not create a physical access into the DUT. This is a zero time access task This task forces the value from the argument list into the ral mirror. It does not create a physical access into the dut. This is a zero time access task All above ral features and some others specified in [1, 2, 3] make writing register and memory test cases anautomatic process The user will find the test is already updated once the spec has been changed and mirror recreated if some basic rules are followed in building the test case or if an existing test case provided along with ral is used as an example. There is no need to manually introduce additional code in the test if all registers or memories have a well predefined behaviour from RaL 1.2.VMM. RAL and vcs release All results published in this paper were obtained using System Verilog language, VMM release 1.3.13.RAL release 1.7.2 and vcs release 2006.06SP1-15 2. RAL implementation in a real verification environment RaL has been deployed in an existing VMM verification environment created around a dut representing a traffic management device as shown in Figure 1 It is known that ral has most productivity impact for complex designs with at least 100 registers At the time ral was deployed on our design the spec was in progress and little was known about the total number of registers. The total number of registers ended up at around 160 which complied with the "100 register rule of thumb for raL. The memory used in the dut had to be modeled as register arrays and tested as such. memory field access was a requirement for the project, so a simple solution to access a memory field without too much manual decoding from the user was needed. With the dut implementing 10 different logical blocks a similar SNUG San josc 2008 A Fully reusable register/Memory Access Solution: USing VMM RAL approach has been followed in defining ral hierarchy since each block in the dUt had its own set of registers and most of the time its own set of memories. The dut implemented memories in 6 out of 10 of its blocks. The size of the each memory ranged from l to 64 Kbytes. The access size into DUT registers/memories was 32 bits(4 bytes). All registers had 32 bit access while the memory was organized into rows with data ranging from 4 to 64 bytes per row. Because of this variety of access sizes parameter from Ral had to be defined in the to be 512(bits)in order for the ral mirror to be properly generated later (i.e ) RAL end users should read [l] for more details about the usage of this parameter including other ways of defining it in an existing VMM environment Based on the complexity of memory sizes and seeing the necessity to decode such a variety of accesses into dUT for every individual memory ral has proven to be a good choice in the end Bascd on the rcquirements of the projcct a couple of ral predefined register acccss types wcrc implemented in the dUT as follows: rw(read/write), rc(read to clear), ro(read only ), wlc (write 1 to clear), wo(write only). Some registers with a different behaviour than RaL predefined types were assigned user or userl types and they were treated as exceptions the automatic test case or tested separately under a special setup based on the name of the register or by the type if all ended up in the same type category. These registers usually determined unexpected behaviour from dut when some bits were written under normal operation. In order to simplify the verification process and debug later on in the development of the project, only one access type per register was allowed for each register or memory modeled as register array. If a new access type was needed in a register another separate register was created in the block As shown in Figure I software access into the dUT was performed via PCI Express bus. The verification environment implemented a PCI Express transactor capable of creating reads and writes from/to dut on the bus. Only a single domain access was used in the verification environment. The Ral model will send read/write transactions to a 3 party PCI Express bus functional model (bfm which will access the registers and memories in the dUt. The Ral model also provides the verification cnvironment with backdoor acccss to the registers and memories modeled as register arrays which will by-pass the physical interface in order to speed up simulations SNUG San josc 2008 A Fully reusable register/Memory Access Solution: USing VMM RAL Figure l RAL implementation in a VMM environment 2. 1. Resources Required to Integrate RaL An cxisting VMM environment is among the first requirements for a ral deployment. Somc minor changes were needed to a classic vmm environment in order to accommodate RaL. the first change is reflected in Figure 2 below, and it refers to the use of vmm ral env base class SNUG San josc 2008 A Fully reusable register/Memory Access Solution: USing VMM RAL instead of classical vmm eny base class in order to create the main vmm environment Basically this creates a Ral aware environment in Vmm. ral needs to be declared next in dut env as the predefined class RAL model is created in the new function of dut env class as shown in Figure 2 Figure 2. Building a RaL aware environment Another challenge was creating a script to translate the spec into ral files [1] accepted by the ynopsys' provided script )to generate the ral model. These two scripts together basically create a translation flow from spec to the ral model The information from every register from the spec needs to be translated into a class with members and tasks/functions operating on the members. This translation is not totally under the user's control. The script which translates from the spcc to the ral files(scc Figurc 1 Figurc 3) is fully under thc user's control because of the large variety of spec formats available. The script is an executable and it takes previously generated ral files as arguments and creates a RaL model (classes)which is not supposed to be altered by the user script to parse the spec and generate RAl files this script is totally under user/s control >gen regs / script to parse previously generated rAl files and generate RAl model //(classes) , this script is an executable created by Synopsys no user control >svCs HOME/bin/ralcen -b -1 sv-t dut name -I ./ral= files -ext ud ut top.xa⊥f Figure 3. Scripts required in Ral integration The ral model is basically the bridge between the spec and the rest of the environment In addition it translates spec changes into automatic testcase updates since it contains the entire documentation written into the object oriented language. Once a process has been put in place to generate RAL files from the spec, the total number of registers in a project becomes irrelevant The script is able to handle as many registers as possiblc as long as the correct syntax and rules SNUG San josc 2008 A Fully reusable register/Memory Access Solution: USing VMM RAL to generate Ral files specified in [1] are followed. However, some issues may appear with regard to the total physical memory usage and computing resources if the number of registers is very high. Also the automatic RaL coverage model for such a memory map may prove challenging to build The final piece needed in Ral integration is a way to connect the above generated ral model to the dut. this is done via existing write/read tasks which the user needs to create in a transactor. The widely known VMM base class vmm actor from a classic vmm verification environment has to be changed only for this particular transactor to vmm rw actor as shown in Figure 4. A RAL required task (ie. execute single())is the main communication point between ral environment and the bfm used in Figure 4. transactor class for writes/reads This unique point of communication between the Ral model and the physical bus gives the user the flexibility to shift addresses generated by ral environment before entering into the bfm Basically the user has full control of addressing into the DUt, matching exactly the internal DUT implementation. This aspect will be detailed later on in the paper in 3. 4 3. RAL Integration Flow: from spec definition to coverage feedback Based on the experience acquired in this project, some general guidelines can be identified before initiating the work with ral Read the ral user guide and fully understand rules to follow in defining the spec in order to comply with some ral requirements. If the recommended rules are not followed there may be limitations as to what can be modeled in RAL Spec definition is essential in success with Ral as the registers and memories should have a standard format that is strictly used throughout the spec Create a script which is able to parse the spec and generate syntax correct ral files Be prepared to follow some guidelines of writing rtl code in dut to comply with some backdoor requirements of RAL Otherwise automatic backdoor capability becomes difficult to implement without extensive churn and rework Change the existing VmM environment as mentioned in Section 2.1 SNUG San josc 2008 A Fully reusable register/Memory Access Solution: USing VMM RAL

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