Lora测温项目源代码

; generated by Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637] ; commandline ArmCC [--list --split_sections --debug -c --asm --interleave -o.\obj\sx1276_7_8.o --asm_dir=.\List\ --list_dir=.\List\ --depend=.\obj\sx1276_7_8.d --cpu=Cortex-M0 --apcs=interwork -O3 --diag_suppress=9931 -I..\CMSIS -I..\STM_Lib\inc -I..\USER -I..\drive -I.\RTE\_Project -IC:\Keil_v5\ARM\PACK\ARM\CMSIS\5.2.0\CMSIS\Include -IC:\Keil_v5\ARM\PACK\Keil\STM32F0xx_DFP\1.5.0\Device\Include -D__MICROLIB -D__UVISION_VERSION=525 -D_RTE_ -DSTM32F030x6 -DUSE_STDPERIPH_DRIVER -DSTM32F0XX --omf_browse=.\obj\sx1276_7_8.crf ..\drive\sx1276_7_8.c] THUMB AREA ||i.Get_SX1278_IRQ_Status||, CODE, READONLY, ALIGN=1 Get_SX1278_IRQ_Status PROC ;;;25 **********************************************/ ;;;26 unsigned char Get_SX1278_IRQ_Status(void) 000000 b510 PUSH {r4,lr} ;;;27 { ;;;28 unsigned char s = 0; ;;;29 ;;;30 s = SPIRead(LR_RegIrqFlags); 000002 2012 MOVS r0,#0x12 000004 f7fffffe BL SPIRead ;;;31 return s; ;;;32 } 000008 bd10 POP {r4,pc} ;;;33 ENDP AREA ||i.hexdump||, CODE, READONLY, ALIGN=2 REQUIRE _printf_pre_padding REQUIRE _printf_percent REQUIRE _printf_flags REQUIRE _printf_widthprec REQUIRE _printf_x REQUIRE _printf_longlong_hex hexdump PROC ;;;33 ;;;34 void hexdump(unsigned char *buf, const int num) 000000 b570 PUSH {r4-r6,lr} ;;;35 { 000002 460d MOV r5,r1 000004 4606 MOV r6,r0 ;;;36 int i; ;;;37 for(i = 0; i < num; i++) 000006 2400 MOVS r4,#0 000008 e004 B |L2.20| |L2.10| ;;;38 { ;;;39 printf("%02X ", buf[i]); 00000a 5d31 LDRB r1,[r6,r4] 00000c a004 ADR r0,|L2.32| 00000e f7fffffe BL __2printf 000012 1c64 ADDS r4,r4,#1 |L2.20| 000014 42ac CMP r4,r5 ;37 000016 dbf8 BLT |L2.10| ;;;40 //if ((i+1)%8 == 0) ;;;41 // printf("\n"); ;;;42 } ;;;43 printf("\n"); 000018 a003 ADR r0,|L2.40| 00001a f7fffffe BL __2printf ;;;44 return; ;;;45 } 00001e bd70 POP {r4-r6,pc} ;;;46 ENDP |L2.32| 000020 25303258 DCB "%02X ",0 000024 2000 000026 00 DCB 0 000027 00 DCB 0 |L2.40| 000028 0a00 DCB "\n",0 00002a 00 DCB 0 00002b 00 DCB 0 AREA ||i.sx1276_7_8_Config||, CODE, READONLY, ALIGN=2 sx1276_7_8_Config PROC ;;;330 **********************************************************/ ;;;331 unsigned char sx1276_7_8_Config(void) 000000 b570 PUSH {r4-r6,lr} ;;;332 { ;;;333 unsigned char s = 0; ;;;334 ;;;335 sx1276_7_8_Sleep(); //Change modem mode Must in Sleep mode 000002 f7fffffe BL sx1276_7_8_Sleep ;;;336 SPIWrite(0x4b,0x09); 000006 2109 MOVS r1,#9 000008 204b MOVS r0,#0x4b 00000a f7fffffe BL SPIWrite ;;;337 //for(i=250;i!=0;i--) //Delay ;;;338 //NOP(); ;;;339 //delay_ms(15); ;;;340 ;;;341 //lora mode ;;;342 sx1276_7_8_EntryLoRa(); 00000e f7fffffe BL sx1276_7_8_EntryLoRa ;;;343 //SPIWrite(0x5904); //?? Change digital regulator form 1.6V to 1.47V: see errata note ;;;344 ;;;345 BurstWrite(LR_RegFrMsb,sx1276_7_8FreqTbl[0],3); //setting frequency parameter 000012 2203 MOVS r2,#3 000014 493b LDR r1,|L3.260| 000016 2006 MOVS r0,#6 000018 f7fffffe BL BurstWrite ;;;346 ;;;347 //setting base parameter ;;;348 SPIWrite(LR_RegPaConfig,sx1276_7_8PowerTbl[Power_Sel]); //Setting output power parameter 00001c 4c39 LDR r4,|L3.260| 00001e 483a LDR r0,|L3.264| 000020 1f24 SUBS r4,r4,#4 000022 7821 LDRB r1,[r4,#0] ; Power_Sel 000024 5c41 LDRB r1,[r0,r1] 000026 2009 MOVS r0,#9 000028 f7fffffe BL SPIWrite ;;;349 ;;;350 SPIWrite(LR_RegOcp,0x0B); //RegOcp,Close Ocp 00002c 210b MOVS r1,#0xb 00002e 4608 MOV r0,r1 000030 f7fffffe BL SPIWrite ;;;351 SPIWrite(LR_RegLna,0x23); //RegLNA,High & LNA Enable 000034 2123 MOVS r1,#0x23 000036 200c MOVS r0,#0xc 000038 f7fffffe BL SPIWrite ;;;352 ;;;353 if(sx1276_7_8SpreadFactorTbl[Lora_Rate_Sel]==6) //SFactor=6 00003c 4d32 LDR r5,|L3.264| 00003e 7860 LDRB r0,[r4,#1] ; Lora_Rate_Sel 000040 1d2d ADDS r5,r5,#4 000042 5c29 LDRB r1,[r5,r0] ;;;354 { ;;;355 unsigned char tmp; ;;;356 SPIWrite(LR_RegModemConfig1,((sx1276_7_8LoRaBwTbl[BandWide_Sel]<<4)+(CR<<1)+0x01));//Implicit Enable CRC Enable(0x02) & Error Coding rate 4/5(0x01), 4/6(0x02), 4/7(0x03), 4/8(0x04) 000044 1de8 ADDS r0,r5,#7 000046 2906 CMP r1,#6 ;353 ;;;357 SPIWrite(LR_RegModemConfig2,((sx1276_7_8SpreadFactorTbl[Lora_Rate_Sel]<<4)+(CRC<<2)+0x03)); ;;;358 ;;;359 tmp = SPIRead(0x31); ;;;360 tmp &= 0xF8; ;;;361 tmp |= 0x05; ;;;362 SPIWrite(0x31,tmp); ;;;363 SPIWrite(0x37,0x0C); ;;;364 } ;;;365 else ;;;366 { ;;;367 SPIWrite(LR_RegModemConfig1,((sx1276_7_8LoRaBwTbl[BandWide_Sel]<<4)+(CR<<1)+0x00));//Explicit Enable CRC Enable(0x02) & Error Coding rate 4/5(0x01), 4/6(0x02), 4/7(0x03), 4/8(0x04) 000048 78a1 LDRB r1,[r4,#2] ; BandWide_Sel 00004a 5c40 LDRB r0,[r0,r1] 00004c d03d BEQ |L3.202| 00004e 0100 LSLS r0,r0,#4 000050 1d00 ADDS r0,r0,#4 000052 b2c1 UXTB r1,r0 000054 201d MOVS r0,#0x1d 000056 f7fffffe BL SPIWrite ;;;368 SPIWrite(LR_RegModemConfig2,((sx1276_7_8SpreadFactorTbl[Lora_Rate_Sel]<<4)+(CRC<<2)+0x03)); //SFactor & LNA gain set by the internal AGC loop 00005a 7860 LDRB r0,[r4,#1] ; Lora_Rate_Sel 00005c 5c28 LDRB r0,[r5,r0] 00005e 0100 LSLS r0,r0,#4 000060 1dc0 ADDS r0,r0,#7 000062 b2c1 UXTB r1,r0 000064 201e MOVS r0,#0x1e |L3.102| 000066 f7fffffe BL SPIWrite ;;;369 } ;;;370 ;;;371 SPIWrite(0x26,0x08); 00006a 2108 MOVS r1,#8 00006c 2026 MOVS r0,#0x26 00006e f7fffffe BL SPIWrite ;;;372 SPIWrite(0x31,0xC5); 000072 21c5 MOVS r1,#0xc5 000074 2031 MOVS r0,#0x31 000076 f7fffffe BL SPIWrite ;;;373 SPIWrite(0x37,0x0c); 00007a 210c MOVS r1,#0xc 00007c 2037 MOVS r0,#0x37 00007e f7fffffe BL SPIWrit