PWM ON FPGA

This report describes the design of a simple Pulse Width Modulator. The design is consists of data path and control path. The data path is consists of counter, a d-register, a comparator, a 2:1 multiplexer. The control path is consists of a controller. The design can output a desired duty cycle and period waveform by inputting a specified value and setting the width of counter, d-register, and equals. The design presented here achieves this function by using a traditional hardware description language VHDL.