AD9520-0
Rev 0 | Page 2 of 84
目录
特性....................................................................................................1
应用....................................................................................................1
概述....................................................................................................1
功能框图...........................................................................................1
修订历史...........................................................................................3
技术规格...........................................................................................4
电源要求......................................................................................4
PLL特性 .......................................................................................4
时钟输入......................................................................................7
时钟输出......................................................................................7
时序特性......................................................................................8
时序图.....................................................................................9
时钟输出加性相位噪声(仅分配;
未使用VCO分频器) ............................................................... 10
时钟输出绝对相位噪声(使用内部VCO)........................... 11
时钟输出绝对时间抖动(使用内部VCO
的时钟产生).............................................................................11
时钟输出绝对时间抖动(使用内部
VCO的时钟净化).................................................................... 11
时钟输出绝对时间抖动(使用外部
VCXO的时钟产生).................................................................12
时钟输出加性时间抖动(未使用
VCO分频器) ............................................................................12
时钟输出加性时间抖动(使用VCO分频器) ......................13
串行控制端口—SPI模式 .......................................................13
串行控制端口—I
2
C模式 .......................................................14
PD, SYNC和RESET引脚........................................................15
串行端口设置引脚:SP1、SP0 ........................................... 15
LD、STATUS和REFMON引脚 ...........................................15
功耗 ...........................................................................................16
绝对最大额定值...........................................................................17
热阻 ...........................................................................................17
ESD警告....................................................................................17
引脚配置和功能描述 ..................................................................18
典型工作特性 ...............................................................................21
术语................................................................................................. 26
详细框图........................................................................................ 27
工作原理........................................................................................ 28
工作配置.........................................................................................28
模式0:内部VCO和时钟分配..............................................28
模式1:时钟分配或外部VCO <1600 MHz ........................30
模式2:高频时钟分配—CLK或外部
VCO > 1600 MHz .....................................................................32
锁相环(PLL) .............................................................................34
PLL配置 .....................................................................................34
鉴频鉴相器(PFD) ...................................................................34
电荷泵(CP) ...............................................................................35
片内VCO ...................................................................................35
PLL外部环路滤波器 ...............................................................35
PLL参考输入.............................................................................35
参考切换....................................................................................36
参考分频器R.............................................................................36
VCO/VCXO反馈分频器N:P、A、B、R.........................36
数字锁定检测(DLD) ..............................................................38
模拟锁定检测(ALD) ..............................................................38
电流源数字锁定检测(CSDLD) ............................................38
外部VCXO/VCO时钟输入(CLK/CLK) ..............................39
保持 ............................................................................................39
外部/手动保持模式.................................................................39
自动/内部保持模式.................................................................39
频率状态监控器.......................................................................41
VCO校准 ...................................................................................42
零延迟操作.....................................................................................43
内部零延迟模式.......................................................................43
外部零延迟模式.......................................................................43
时钟分配.........................................................................................44
工作模式....................................................................................44
CLK或VCO直接至LVPECL输出..........................................44
时钟分频....................................................................................45
VCO分频器...............................................................................45
通道分频器 ...............................................................................45
同步输出—SYNC功能............................................................47
LVPECL输出驱动器................................................................49
CMOS输出驱动器 ...................................................................49