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DS255 March 1, 2011 www.xilinx.com 1
Product Specification
© Copyright 2003-2011, Xilinx, Inc. XILINX, the Xilinx logo, ISE, Kintex, Spartan, Virtex, and other designated brands included herein are trademarks of Xilinx in the
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Introduction
The Xilinx LogiCORE™ IP Multiplier implements
high-performance, optimized multipliers. A number of
resource and performance trade-off options are
available to tailor the core to a particular application.
Features
• Drop-in module for Virtex
®
-7 and Kintex™-7,
Virtex-6, Virtex-5, Virtex-4, Spartan
®
-6,
Spartan-3/XA, Spartan-3E/XA,
Spartan-3A/3AN/3A DSP/XA FPGAs
• Generates fixed-point parallel multipliers and
constant-coefficient multipliers for two’s
complement signed or unsigned data
• Supports inputs ranging from 1 to 64 bits wide and
outputs ranging from 1 to 128 bits wide with any
portion of the full product selectable
• Configurable latency for all multiplier variants
• Resource estimation in the Xilinx CORE
Generator™ graphical user interface (GUI)
• Supports symmetric rounding to infinity for Virtex
and Kintex device multipliers when using the
XtremeDSP™ slice
• For use with Xilinx CORE Generator and Xilinx
System Generator for DSP 13.1
LogiCORE IP Multiplier v11.2
DS255 March 1, 2011 Product Specification
LogiCORE IP Facts Table
Core Specifics
Supported
Device Family
(1)
1. For a complete listing of supported devices, see the release notes
for this core.
Virtex-7 and Kintex-7
Virtex-6, Virtex-5, Virtex-4,
Spartan-6, Spartan-3/XA, Spartan-3E/XA,
Spartan-3A/3AN/3A DSP/XA
Supported User
Interfaces
Not Applicable
Resources
(2)
2. Resources listed here are for Virtex-6 devices. For more complete
device performance numbers, see Performance and Resource
Utilization, page 7.
Frequency
Configuration LUTs FFs
DSP
Slices
Block
RAMs
Max. Freq.
9x9, Use LUTs,
Speed
optimized
115 110 0 0 450 MHz
25x18, Use
Mults, Speed
optimized
0 0 1 0 450 MHz
Provided with Core
Documentation Product Specification
Design Files Netlist
Example Design Not Provided
Test Bench Not Provided
Constraints File Not Applicable
Simulation
Model
VHDL behavioral model in the xilinxcorelib library
VHDL UniSim structural model
Verilog UniSim structural model
Tested Design Tools
Design Entry
Tools
CORE Generator 13.1
System Generator for DSP 13.1
Simulation
Mentor Graphics ModelSim 6.6d
Cadence Incisive Enterprise Simulator (IES) 10.2
Synopsys VCS and VCS MX 2010.06
ISIM 13.1
Synthesis Tools N/A
Support
Provided by Xilinx, Inc.