verilog编写的1024点的fft快速傅立叶变换代码

1024点的t快速傅立叶变换verilog代码

`timescale 1 ns / 1 ns

module cf_t_1024_8 (clock_c, enable_i, reset_i, sync_i, data_0_i, data_1_i, sync_o,

data_0_o, data_1_o);

input clock_c;

input enable_i;

input reset_i;

input sync_i;

wire [15:0] n2;

wire [15:0] n3;

cf_t_1024_8_1 s1 (clock_c, sync_i, data_0_i, data_1_i, enable_i, reset_i, n1, n2, n3);

assign sync_o = n1;

assign data_0_o = n2;

assign data_1_o = n3;

endmodule

module cf_t_1024_8_1 (clock_c, i1, i2, i3, i4, i5, o1, o2, o3);

input clock_c;

input i1;

output [15:0] o3;

wire s1_1;

wire [15:0] s1_2;

wire [15:0] s1_3;

wire s2_1;

wire [15:0] s2_2;

wire [15:0] s2_3;

wire s3_1;

wire [15:0] s3_2;

wire [15:0] s3_3;

cf_t_1024_8_2 s4 (clock_c, i1, i2, i3, i4, i5, s4_1, s4_2, s4_3);

assign o3 = s2_3;

assign o2 = s2_2;

assign o1 = s2_1;

endmodule

module cf_t_1024_8_2 (clock_c, i1, i2, i3, i4, i5, o1, o2, o3);

input clock_c;

input i1;

input [15:0] i2;

input [15:0] i3;

wire n2;

wire n3;

wire [7:0] n4;

wire [7:0] n5;

wire [1:0] n6;

wire [15:0] n7;

wire [15:0] n8;

wire [15:0] n9;

wire [15:0] n10;

wire [15:0] n11;

wire [8:0] s16_1;

wire s16_2;

assign n1 = {i2, i3};

assign n2 = s16_1[8];

assign n3 = ~n2;

assign n4 = {s16_1[7],

s16_1[6],

s16_1[5],

s16_1[4],

s16_1[3],

n4[3],

n4[4],

n4[5],

n4[6],

n4[7]};

assign n6 = {s15_2, s15_1};

assign n7 = {s15_3[31],

s15_3[30],

s15_3[29],

s15_3[28],

s15_3[24],

s15_3[23],

s15_3[22],

s15_3[21],

s15_3[14],

s15_3[13],

s15_3[12],

s15_3[11],

s15_3[10],

s15_3[9],

s15_3[8],

s15_3[7],

s15_3[6],

s15_3[5],

s14_1[30],

s14_1[29],

s14_1[28],

s14_1[27],

s14_1[26],

s14_1[25],

s14_1[24],

s14_1[23],

s14_1[22],

s14_1[21],

s14_1[14],

s14_1[13],

s14_1[12],

s14_1[11],

s14_1[10],

s14_1[9],

s14_1[8],

s14_1[7],

s14_1[6],

s14_1[5],

s14_1[1],

s14_1[0]};

assign n11 = s13_1 ? n8 : n7;

assign n12 = s13_1 ? n10 : n9;

assign o1 = s15_1;

endmodule

module cf_t_1024_8_3 (clock_c, i1, i2, i3, i4, i5, i6, o1, o2, o3);

input clock_c;

input i1;

input [31:0] i2;

input i3;

input [7:0] i4;

input i5;

reg [7:0] n3;

wire n4;

reg n5;

wire [7:0] n6;

wire n7;

wire n8;

wire [31:0] n9;

reg [7:0] n9a;

reg [31:0] n9m [255:0];

wire n10;

wire s15_1;

assign n1 = 8'b00000001;

assign n2 = n3 + n1;

initial n3 = 8'b00000000;

always @ (posedge clock_c)

if (n14 == 1'b1)

n3 <= 8'b00000000;

else if (i5 == 1'b1)

n3 <= n2;

assign n4 = ~s15_1;

n5 <= 1'b0;

else if (i5 == 1'b1)

n5 <= i1;

assign n6 = 8'b00000000;

n9m[i4] <= i2;

n9a <= n3;

end

assign n9 = n9m[n9a];

assign n10 = i3 & s15_1;

initial n11a = 8'b00000000;

always @ (posedge clock_c)

if (i5 == 1'b1) begin

if (n10 == 1'b1)

n11m[i4] <= i2;

n12 <= 1'b0;

else if (i5 == 1'b1)

n12 <= n4;

assign n13 = n12 ? n11 : n9;

assign n14 = i1 | i6;

cf_t_1024_8_30 s15 (clock_c, i1, i5, i6, s15_1);

assign o3 = n13;

assign o2 = n7;

assign o1 = n5;

endmodule

input [7:0] i4;

input i5;

input i6;

output [31:0] o1;

wire [7:0] n1;

wire [7:0] n2;

reg [7:0] n3;

wire n4;

wire n5;

wire [31:0] n6;