沁恒CH32V30X学习笔记11-使用外部时钟模式2采集脉冲计数

/********************************** (C) COPYRIGHT ******************************* * File Name : ch32v30x_tim.c * Author : WCH * Version : V1.0.0 * Date : 2021/06/06 * Description : This file provides all the TIM firmware functions. ********************************************************************************* * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. * Attention: This software (modified or not) and binary are used for * microcontroller manufactured by Nanjing Qinheng Microelectronics. *******************************************************************************/ #include "ch32v30x_tim.h" #include "ch32v30x_rcc.h" /* TIM registers bit mask */ #define SMCFGR_ETR_Mask ((uint16_t)0x00FF) #define CHCTLR_Offset ((uint16_t)0x0018) #define CCER_CCE_Set ((uint16_t)0x0001) #define CCER_CCNE_Set ((uint16_t)0x0004) static void TI1_Config(TIM_TypeDef *TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, uint16_t TIM_ICFilter); static void TI2_Config(TIM_TypeDef *TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, uint16_t TIM_ICFilter); static void TI3_Config(TIM_TypeDef *TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, uint16_t TIM_ICFilter); static void TI4_Config(TIM_TypeDef *TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, uint16_t TIM_ICFilter); /********************************************************************* * @fn TIM_DeInit * * @brief Deinitializes the TIMx peripheral registers to their default * reset values. * * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. * * @return none */ void TIM_DeInit(TIM_TypeDef *TIMx) { if(TIMx == TIM1) { RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM1, ENABLE); RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM1, DISABLE); } else if(TIMx == TIM8) { RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM8, ENABLE); RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM8, DISABLE); } else if(TIMx == TIM9) { RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM9, ENABLE); RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM9, DISABLE); } else if(TIMx == TIM10) { RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM10, ENABLE); RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM10, DISABLE); } else if(TIMx == TIM2) { RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, ENABLE); RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, DISABLE); } else if(TIMx == TIM3) { RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, ENABLE); RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, DISABLE); } else if(TIMx == TIM4) { RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM4, ENABLE); RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM4, DISABLE); } else if(TIMx == TIM5) { RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM5, ENABLE); RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM5, DISABLE); } else if(TIMx == TIM6) { RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM6, ENABLE); RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM6, DISABLE); } else if(TIMx == TIM7) { RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM7, ENABLE); RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM7, DISABLE); } } /********************************************************************* * @fn TIM_TimeBaseInit * * @brief Initializes the TIMx Time Base Unit peripheral according to * the specified parameters in the TIM_TimeBaseInitStruct. * * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. * TIM_TimeBaseInitStruct - pointer to a TIM_TimeBaseInitTypeDef * structure. * * @return none */ void TIM_TimeBaseInit(TIM_TypeDef *TIMx, TIM_TimeBaseInitTypeDef *TIM_TimeBaseInitStruct) { uint16_t tmpcr1 = 0; tmpcr1 = TIMx->CTLR1; if((TIMx == TIM1) || (TIMx == TIM2) || (TIMx == TIM3) || (TIMx == TIM4) || (TIMx == TIM5) || (TIMx == TIM8) || (TIMx == TIM9) || (TIMx == TIM10)) { tmpcr1 &= (uint16_t)(~((uint16_t)(TIM_DIR | TIM_CMS))); tmpcr1 |= (uint32_t)TIM_TimeBaseInitStruct->TIM_CounterMode; } if((TIMx != TIM6) && (TIMx != TIM7)) { tmpcr1 &= (uint16_t)(~((uint16_t)TIM_CTLR1_CKD)); tmpcr1 |= (uint32_t)TIM_TimeBaseInitStruct->TIM_ClockDivision; } TIMx->CTLR1 = tmpcr1; TIMx->ATRLR = TIM_TimeBaseInitStruct->TIM_Period; TIMx->PSC = TIM_TimeBaseInitStruct->TIM_Prescaler; if((TIMx == TIM1) || (TIMx == TIM8) || (TIMx == TIM9) || (TIMx == TIM10)) { TIMx->RPTCR = TIM_TimeBaseInitStruct->TIM_RepetitionCounter; } TIMx->SWEVGR = TIM_PSCReloadMode_Immediate; } /********************************************************************* * @fn TIM_OC1Init * * @brief Initializes the TIMx Channel1 according to the specified * parameters in the TIM_OCInitStruct. * * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. * TIM_OCInitStruct - pointer to a TIM_OCInitTypeDef structure. * * @return none */ void TIM_OC1Init(TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct) { uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0; TIMx->CCER &= (uint16_t)(~(uint16_t)TIM_CC1E); tmpccer = TIMx->CCER; tmpcr2 = TIMx->CTLR2; tmpccmrx = TIMx->CHCTLR1; tmpccmrx &= (uint16_t)(~((uint16_t)TIM_OC1M)); tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CC1S)); tmpccmrx |= TIM_OCInitStruct->TIM_OCMode; tmpccer &= (uint16_t)(~((uint16_t)TIM_CC1P)); tmpccer |= TIM_OCInitStruct->TIM_OCPolarity; tmpccer |= TIM_OCInitStruct->TIM_OutputState; if((TIMx == TIM1) || (TIMx == TIM8) || (TIMx == TIM9) || (TIMx == TIM10)) { tmpccer &= (uint16_t)(~((uint16_t)TIM_CC1NP)); tmpccer |= TIM_OCInitStruct->TIM_OCNPolarity; tmpccer &= (uint16_t)(~((uint16_t)TIM_CC1NE)); tmpccer |= TIM_OCInitStruct->TIM_OutputNState; tmpcr2 &= (uint16_t)(~((uint16_t)TIM_OIS1)); tmpcr2 &= (uint16_t)(~((uint16_t)TIM_OIS1N)); tmpcr2 |= TIM_OCInitStruct->TIM_OCIdleState; tmpcr2 |= TIM_OCInitStruct->TIM_OCNIdleState; } TIMx->CTLR2 = tmpcr2; TIMx->CHCTLR1 = tmpccmrx; TIMx->CH1CVR = TIM_OCInitStruct->TIM_Pulse; TIMx->CCER = tmpccer; } /********************************************************************* * @fn TIM_OC2Init * * @brief Initializes the TIMx Channel2 according to the specified * parameters in the TIM_OCInitStruct. * * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. * TIM_OCInitStruct - pointer to a TIM_OCInitTypeDef structure. * * @return none */ void TIM_OC2Init(TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct) { uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0; TIMx->CCER &= (uint16_t)(~((uint16_t)TIM_CC2E)); tmpccer = TIMx->CCER; tmpcr2 = TIMx->CTLR2; tmpccmrx = TIMx->CHCTLR1; tmpccmrx &= (uint16_t)(~((uint16_t)TIM_OC2M)); tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CC2S)); tmpccmrx |= (uint16_t)(TIM_OCInitStruct->TIM_OCMode << 8); tmpccer &= (uint16_t)(~((uint16_t)TIM_CC2P)); tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 4); tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 4); if((TIMx == TIM1) || (TIMx == TIM8) || (TIMx == TIM9) || (TIMx == TIM10)) { tmpccer &= (uint16_t)(~((uint16_t)TIM_CC2NP)); tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCNPolarity << 4); tmpccer &= (uint16_t)(~((uint16_t)TIM_CC2NE)); tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputNState << 4); tmpcr2 &=