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The Features of
S3C6410
S3C6400 vs. S3C6410
OCT 30, 2007
REV 0.2
S3C6400 VS S3C6410
2
IMPORTANT NOTICE
The information in this publication has been carefully
checked and is believed to be entirely accurate at the
time of publication. Samsung assumes no
responsibility, however, for possible errors or
omissions, or for any consequences resulting from the
use of the information contained herein.
Samsung reserves the right to make changes in its
products or product specifications with the intent to
improve function or design at any time and without
notice and is not required to update this
documentation to reflect such changes.
This publication does not convey to a purchaser of
semiconductor devices described herein any license
under the patent rights of Samsung or others.
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guarantee regarding the suitability of its products for
any particular purpose, nor does Samsung assume
any liability arising out of the application or use of any
product or circuit and specifically disclaims any and all
liability, including without limitation any consequential
or incidental damages.
“Typical” parameters can and do vary in different
applications. All operating parameters, including
“Typicals” must be validated for each customer
application by the customer’s technical experts.
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.
S3C6410 32-Bit Risc Microcontroller
Copyright © 2007 Samsung Electronics Co.,Ltd.
All rights reserved. No part of this publication may be reproduced, stored in a retrieval system, or transmitted in
any form or by any means, electric or mechanical, by photocopying, recording, or otherwise, without the prior
written consent of Samsung Electronics Co.,Ltd.
Samsung Electronics Co., Ltd.
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Printed in the Republic of Korea
S3C6400 VS S3C6410
3
C
C
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
Revision History
Revision No Description of Change Refer to Author(s) Date
0.1 - Initial Release for review - AUG 01, 2007
0.2 -Added SYSCON & GPIO OCT 30, 2007
S3C6400 VS S3C6410
4
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
1. OVERVIEW (A POINT OF DIFFERENCE)
S3C6400 S3C6410 (Added IP & function) S/W change
DMC
Improved pipeline stages
Deep Power Down support
Variable number of auto-refresh requests
before priority change.
Improved write termination
Auto self refresh entry
1.bank_bits is fixed for 4
banks
2. except 1, new controls
are implemented in
reserved addresses and
bits
Lowest 2 bit of address bit is ignored
when accessed with AHB memory
channel.
Lowest 4 bit of address bit is ignored when
accessed with AHB memory channel.
Address map for
accessing OneNAND
memory contents is
different.
Maximum burst length of four is
supported when accessing through
AHB memory access channel.
Maximum burst length of eight is supported
when accessing through AHB memory access
channel.
OneNANDC
OneNAND controller has a separate
clock domain other than AHB clock
domain.
OneNAND controller shares AHB clock domain
with other memory controllers.
NFCON
4KB Stepping Stone
1/4bit HW ECC
512B/2KB page read
8KB Stepping Stone
1/4/8-bit HW ECC
512B/2K/4KB page read
6400 Compatible
Spare ECC generation (8-
bit)
CFCON
CFCON 4.0
CFCON 4.01
HREADY Bug Fix
6400 Compatible
DMAC
MODEM_IF DMA operation not
supported
Support MODEM_IF DMA (Mem-to-Mem) New SFRs added
VIC
Interrupt source Interrupt source
Display
CON
FIMD 4.0
FIMD 4.2.1
ITU BT.601/656 interface
FIMC local interface sync clock addition
6400 Compatible
2D
FIMG-2D 1.23
FIMG-2D 2.0
AXI Master
Enhanced Performance
Not Compatible 6400
CAMIF
FIMC 3.0
FIMC 3.2
Preview Path Line Buffer for D1
Support Interlace input
FIMC local interface sync clock addition
MODE IF
DMA operation not supported DMA operation supported New SFRs added
USB OTG
Power Save mode supported
Power Save mode not supported
OTG block power down supported
S/W compatible
S3C6400 VS S3C6410
5
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Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
HSMMC
HSMMC(Ver3.1)
(support SD Host Controller spec
Ver1.0)
HSMMC (Ver4.0)
(support SD Host Controller spec Ver2.0)
New SFRs added
IIC
1ch
2ch
UART
4ch 4ch (3Mbps)
RTC
Tick clock source is 32768Hz
Tick counter is 16bit
Tick clock source
(32768/16384/8192/4096/2048/1024/512/256/1
28/64/32/16/8/4/2/1)
S/W compatible.
IIS 16bit I2S 2ea
24bit Stereo I2S 2ea + 24bit Multi-
Channel(up to 5.1) I2S 1ea
Bit length setting /
Multi-Channel I2S
transmission setting
TSADC 10bit 8channel 12bit 8channel S/W compatible.
3D New
Note)
1. S/W change: User must change the software in S3C6410 even though user wants to use the same
function of S3C6400 (refer to respective chapter in detail)
2. If user would like to use new IP or function, it is necessary to change software
3. There is no software change except above items
