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Multi-Corner Multi-Mode Synthesis in Design Compiler

- A Must or just Nice to Have?

Bernhard M. Riess

Infineon Technologies AG

Am Campeon 1 – 12

D-85579 Munich

bernhard.riess@infineon.com

ABSTRACT

The traditional design flow uses a common constraining – typically named umbrella constraining

– for design implementation, while in the final timing sign-off the design is verified in every

individual mode and corner of operation. Later on, multi-corner multi-mode (MCMM) was made

available and applied in IC Compiler®. Since the 2008.09 release of Design Compiler®,

MCMM is now also available in logic synthesis. In this paper we will apply MCMM constraining

in logic synthesis with Design Compiler®.

Objective of this work is to analyze and evaluate benefits and drawbacks of multi-corner multi-

mode synthesis in Design Compiler®. To do this we synthesize a 170k standard cell testcase in

umbrella mode and MCMM style. In MCMM style 2 – 5 scenarios are applied. The resulting

netlist is placed and routed in IC Compiler®, again either in umbrella or MCMM style. Finally,

the resulting timing is analyzed in PrimeTime® and the obtained results with respect to timing,

area, and power are compared.

Our experiments show that using the MCMM feature of Design Compiler® does not improve

final quality of results. Timing and area results just depend on the modes and corners active in IC

Compiler®, but do not depend on the applied scenarios in Design Compiler®. Moreover, using

additional scenarios in Design Compiler® increases cpu-time and memory requirements. Benefit

of using MCMM in Design Compiler® is definitely the consistency of the applied constraints

throughout the implementation flow. Additionally, using MCMM in Design Compiler® enables

the user to identify timing critical paths and scenarios early in the implementation phase. In

conclusion, we recommend some criteria to the user to ease decision making for or against usage

of MCMM in Design Compiler® dependent on project characteristics.

SNUG Europe 2011 Multi-Corner Multi-Mode Synthesis in Design Compiler 2

Table of Contents

1.0

Introduction .......................................................................................................................... 3

2.0

Design Characteristics.......................................................................................................... 4

3.0

Design Flow and Methodology ............................................................................................ 5

3.1

Chip Modes .................................................................................................................................................. 5

3.2

Chip Corners ................................................................................................................................................ 5

3.3

Resulting Scenarios ...................................................................................................................................... 5

3.4

Logic Synthesis ............................................................................................................................................ 6

3.5

Automatic Place and Route .......................................................................................................................... 8

3.6

Static Timing Analysis ................................................................................................................................. 9

4.0

Results .................................................................................................................................. 9

4.1

Logic Synthesis Results ................................................................................................................................ 9

4.2

Place and Route Results ............................................................................................................................. 11

4.3

Static Timing Analysis Results ................................................................................................................... 14

5.0

Conclusions and Recommendations .................................................................................. 16

5.1

Conclusions ................................................................................................................................................ 16

5.2

Project Recommendations .......................................................................................................................... 16

5.3

Enhancement Request towards Synopsys ................................................................................................... 17

6.0

Acknowledgements ............................................................................................................ 17

Table of Figures

Figure 1: Floorplan of the design .................................................................................................... 4

Figure 2: Definition of scenarios: Example for scenario mission_WORST ................................... 6

Figure 3: Definition of scenarios: mcmm_setup.tcl ........................................................................ 7

Figure 4: Overview on the performed experiments ........................................................................ 8

Table of Tables

Table 1: Logic Synthesis results for all scenarios ........................................................................... 9

Table 2: Automatic place and route timing results for all scenarios ............................................. 11

Table 3: Automatic place and route results w.r.t. power, utilization, runtime, and memory for all

scenarios ................................................................................................................................. 13

Table 4: Static timing analysis results for all scenarios ................................................................ 14

SNUG Europe 2011 Multi-Corner Multi-Mode Synthesis in Design Compiler 3

1.0 Introduction

While static timing analysis (STA) with PrimeTime®(*) (PT) is always analyzing each

individual mode and corner of a design in an individual run (or in case of distributed multi

scenario analysis (DMSA) in a separate subprocess), the traditional implementation flow applies

one common constraining – frequently called umbrella mode constraining – for all modes and

corners of the design. This limitation mainly imposed by the incapability of the implementation

tools Design Compiler®(**) (DC) and IC Compiler®(***) (ICC) is overcome now. Design

Compiler® can handle multiple constraint sets and optimize for multiple corners (multi-mode

multi-corner (MCMM)) since version 2008.09. The same holds for IC Compiler® since release

2005.12.

Appling all modes and corners from the very beginning in the implementation flow promises

several advantages. The full design flow including DC, ICC, and PT can use the same constraint

sets for implementation and timing sign-off. Moreover, DC and ICC can fully optimize the

design for all modes and corners it will later operate in. First, this eliminates the effort to create

individual sign-off constraints for each and every mode for STA and umbrella mode constraints

for design implementation. Second, this methodology should improve timing closure as the

design is optimized for all corners and modes from the very beginning. Third, defining an

individual set of constraints for each mode of the design saves the efforts of identifying all the

false and multicycle paths caused by interference of the various clock systems of all the modes

contained in an umbrella mode constraining. Finally, applying all scenarios in logic synthesis

should improve timing predictability, as critical path and/or scenarios can be identified early in

the implementation flow.

While usage of MCMM in ICC is – due to its earlier availability by Synopsys - established

methodology, application of MCMM in DC is not very popular yet. In this paper we evaluate the

ability of DC to handle designs in MCMM methodology. Moreover, we analyze, whether

MCMM usage in DC helps to improve timing closure and quality of results.

To do this we synthesize a 170k standard cell testcase in umbrella and MCMM style. In MCMM

style 2 – 5 modes/corners (scenarios) are applied. The resulting netlist is placed and routed in

ICC, again either in umbrella or MCMM style. Finally, the resulting timing is analyzed in PT and

the obtained results are compared.

The paper is organized as follows. In the next section the testcase we use to compare umbrella

mode synthesis to MCMM synthesis is characterized. In Chapter 3 the applied design flow and

methodology are presented. The results of the traditional umbrella synthesis flow compared to

the new MCMM flow obtained in logic synthesis, place and route, and static timing analysis are

shown in Chapter 4. Finally, we summarize benefits and drawbacks of MCMM usage in DC and

draw conclusions and recommendations for the user community.

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药罐子也有未来

2023-07-26

: 我对这篇文件的研究方法和实验结果印象深刻，它为设计合成领域带来了新的思路和启发。
赵小杏儿

2023-07-26

: 这是一篇具有实用价值的文件，提供了一个可行的多角度多模态综合的工具和方法，使设计师能够更好地完成其任务。
独角兽邹教授

2023-07-26

: 这篇文件站在实际需求的角度出发，提出了一种有效解决多角度多模态综合难题的方法，非常值得借鉴和探讨。
华亿

2023-07-26

: 该文件通过质朴的语言描述了多角度多模态综合的技术及其在实际设计中的应用，具有较高的实用性。
张匡龙

2023-07-26

: 这篇文件提供了一个全面的多角度多模态综合解决方案，能够满足设计师在实际应用中的需求。

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