© November 2008 Altera Corporation Quartus II Handbook Version 8.1 Volume 1: Design and Synthesis
6. Recommended HDL Coding Styles
Introduction
HDL coding styles can have a significant effect on the quality of results that you
achieve for programmable logic designs. Synthesis tools optimize HDL code for both
logic utilization and performance. However, sometimes the best optimizations require
human understanding of the design, and synthesis tools have no information about
the purpose or intent of the design. You are often in the best position to improve your
quality of results.
This chapter addresses HDL coding style recommendations to ensure optimal
synthesis results when targeting Altera
®
devices, including the following sections:
■ “Quartus II Language Templates” on page 6–1
■ “Using Altera Megafunctions” on page 6–2
■ “Instantiating Altera Megafunctions in HDL Code” on page 6–3
■ “Inferring Multiplier and DSP Functions from HDL Code” on page 6–6
■ “Inferring Memory Functions from HDL Code” on page 6–11
■ “Coding Guidelines for Registers and Latches” on page 6–34
■ “General Coding Guidelines” on page 6–44
■ “Designing with Low-Level Primitives” on page 6–68
f For additional guidelines about structuring your design, refer to the Design
Recommendations for Altera Devices and the Quartus II Design Assistant chapter in
volume 1 of the Quartus II Handbook. For additional hand-crafted techniques you can
use to optimize design blocks for the adaptive logic modules (ALMs) in many Altera
devices, including a collection of circuit building blocks and related discussions, refer
to the Advanced Synthesis Cookbook: A Design Guide for Stratix II and Stratix III Devices.
For style recommendations, options, or HDL attributes specific to your synthesis tool
(including Quartus
®
II Integrated Synthesis and other EDA tools), refer to the tool
vendor’s documentation or the appropriate chapter in the Synthesis section in
volume 1 of the Quartus II Handbook.
Quartus II Language Templates
The Quartus II software provides Verilog HDL, VHDL, AHDL, Tcl script, and
megafunction language templates that can help you with your design.
Many of the Verilog HDL and VHDL examples in this document correspond with
examples in the templates. You can easily insert examples from this document into
your HDL source code using the Insert Template dialog box in the Quartus II user
interface, shown in Figure 6–1.
QII51007-8.1.0
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