altera推荐的代码风格资源-CSDN文库

需积分: 9 103 浏览量 2009-08-16 20:12:59 上传评论收藏 811KB PDF 举报

### Altera推荐的HDL编码风格在设计可编程逻辑器件的过程中，硬件描述语言（HDL）编码风格对于实现高效的设计结果至关重要。本章节详细介绍了Altera推荐的HDL编码风格指南，旨在帮助设计师们更好地优化针对Altera设备的设计。 #### 1. Quartus II 语言模板 Quartus II 软件提供了多种语言模板，包括Verilog HDL、VHDL、AHDL、Tcl脚本以及megafunction语言模板，这些模板能够有效地辅助设计师完成设计工作。使用这些模板可以帮助确保设计的一致性和标准化，并且可以显著提高设计效率。许多在文档中的Verilog HDL和VHDL示例都与提供的模板相匹配，这样用户可以直接将文档中的示例插入到自己的HDL代码中，方便快捷地进行参考和应用。 #### 2. 使用Altera Megafunctions Altera Megafunctions是预先设计好的模块，用于加速复杂设计的实现过程。通过使用这些预先定义的函数，设计师可以避免重新发明轮子，节省时间和资源。此外，它们通常经过了严格的测试和验证，可以确保更高的可靠性。 #### 3. 在HDL代码中实例化Altera Megafunctions 为了在设计中利用Altera Megafunctions，设计师需要了解如何在HDL代码中正确地实例化这些功能。这通常涉及到理解每个Megafunction的接口及其参数设置。文档中详细介绍了实例化的步骤和最佳实践，例如正确的端口映射和信号类型选择等。 #### 4. 从HDL代码推断乘法器和DSP功能乘法器和数字信号处理(DSP)功能在许多现代设计中非常常见。Altera提供了特定的技术来推断这些功能，以便更有效地实现它们。通过遵循推荐的编码风格，设计师可以使合成工具更容易识别这些功能，从而获得更好的性能和资源利用率。 #### 5. 从HDL代码推断存储器功能类似地，存储器功能也是许多设计的关键部分。通过采用推荐的编码方式，可以确保这些功能被正确地推断出来，并且能够在目标设备上实现最优的结果。文档详细解释了如何编写代码以确保合成工具能正确识别和实现各种类型的存储器。 #### 6. 寄存器和锁存器的编码指南寄存器和锁存器在数字系统设计中扮演着重要的角色。正确的使用方法对于实现高性能和低功耗的设计至关重要。本节详细介绍了如何根据具体需求选择合适的寄存器或锁存器，并提供了编码技巧以避免常见的陷阱。 #### 7. 一般编码指南除了特定于某些功能的指南外，文档还提供了一系列通用的编码建议。这些指南适用于所有类型的HDL设计，涵盖了从变量命名约定到模块组织的最佳实践等多个方面。 #### 8. 使用低级原语进行设计对于那些需要更细粒度控制的应用，文档还介绍了一些使用Altera设备中的低级原语进行设计的方法。这些技术通常需要对底层架构有更深的理解，但可以带来更高的灵活性和定制性。 #### 结论 Altera推荐的HDL编码风格覆盖了从基本的编码习惯到高级的优化技巧，旨在帮助设计师充分利用Quartus II软件和其他EDA工具的功能。通过遵循这些指南，设计师不仅能够提高设计质量，还可以减少调试时间和成本，最终实现更加可靠和高效的电子系统。对于想要进一步深入了解特定主题的读者，文档还提供了额外的参考资料，如《Altera Devices Design Recommendations》和《Quartus II Design Assistant》章节等。

资源推荐

资源详情

资源评论

6. Recommended HDL Coding Styles

Introduction

HDL coding styles can have a significant effect on the quality of results that you

achieve for programmable logic designs. Synthesis tools optimize HDL code for both

logic utilization and performance. However, sometimes the best optimizations require

human understanding of the design, and synthesis tools have no information about

the purpose or intent of the design. You are often in the best position to improve your

quality of results.

This chapter addresses HDL coding style recommendations to ensure optimal

synthesis results when targeting Altera

devices, including the following sections:

■ “Quartus II Language Templates” on page 6–1

■ “Using Altera Megafunctions” on page 6–2

■ “Instantiating Altera Megafunctions in HDL Code” on page 6–3

■ “Inferring Multiplier and DSP Functions from HDL Code” on page 6–6

■ “Inferring Memory Functions from HDL Code” on page 6–11

■ “Coding Guidelines for Registers and Latches” on page 6–34

■ “General Coding Guidelines” on page 6–44

■ “Designing with Low-Level Primitives” on page 6–68

f For additional guidelines about structuring your design, refer to the Design

Recommendations for Altera Devices and the Quartus II Design Assistant chapter in

volume 1 of the Quartus II Handbook. For additional hand-crafted techniques you can

use to optimize design blocks for the adaptive logic modules (ALMs) in many Altera

devices, including a collection of circuit building blocks and related discussions, refer

to the Advanced Synthesis Cookbook: A Design Guide for Stratix II and Stratix III Devices.

For style recommendations, options, or HDL attributes specific to your synthesis tool

(including Quartus

II Integrated Synthesis and other EDA tools), refer to the tool

vendor’s documentation or the appropriate chapter in the Synthesis section in

volume 1 of the Quartus II Handbook.

Quartus II Language Templates

The Quartus II software provides Verilog HDL, VHDL, AHDL, Tcl script, and

megafunction language templates that can help you with your design.

Many of the Verilog HDL and VHDL examples in this document correspond with

examples in the templates. You can easily insert examples from this document into

your HDL source code using the Insert Template dialog box in the Quartus II user

interface, shown in Figure 6–1.

QII51007-8.1.0

Chapter 6: Recommended HDL Coding Styles 6–3

Instantiating Altera Megafunctions in HDL Code

In cases where you prefer to use generic HDL code instead of instantiating a

megafunction, follow the guidelines and coding examples in “Inferring Multiplier

and DSP Functions from HDL Code” on page 6–6 and “Inferring Memory Functions

from HDL Code” on page 6–11 to ensure your HDL code infers the appropriate Altera

megafunction.

1 You must use megafunctions to access some Altera device-specific architecture

features. You can infer or instantiate megafunctions to target some features such as

memory and DSP blocks. You must instantiate megafunctions to target certain device

and high-speed features such as LVDS drivers, PLLs, transceivers, and double-data

rate input/output (DDIO) circuitry.

For some designs, generic HDL code can provide better results than instantiating a

megafunction. Refer to the following general guidelines and examples that describe

when to use standard HDL code and when to use megafunctions:

■ For simple addition or subtraction functions, use the + or – symbol instead of an

LPM function. Instantiating an LPM function for simple arithmetic operations can

result in a less efficient result because the function is hard coded and the synthesis

algorithms cannot take advantage of basic logic optimizations.

■ For simple multiplexers and decoders, use array notation (such as out =

data[sel]) instead of an LPM function. Array notation works very well and has

simple syntax. You can use the lpm_mux function to take advantage of

architectural features such as cascade chains in APEX

™

series devices, but use the

LPM function only if you understand the device architecture in detail and want to

force a specific implementation.

■ Avoid division operations where possible. Division is an inherently slow

operation. Many designers use multiplication creatively to produce division

results.

Instantiating Altera Megafunctions in HDL Code

The following sections describe how to use megafunctions by instantiating them in

your HDL code with the following methods:

■ “Instantiating Megafunctions Using the MegaWizard Plug-In Manager”—You can

use the MegaWizard

Plug-In Manager to parameterize the function and create a

wrapper file.

■ “Creating a Netlist File for Other Synthesis Tools”—You can optionally create a

netlist file instead of a wrapper file.

■ “Instantiating Megafunctions Using the Port and Parameter Definition”—You can

instantiate the function directly in your HDL code.

6–4 Chapter 6: Recommended HDL Coding Styles

Instantiating Altera Megafunctions in HDL Code

Quartus II Handbook Version 8.1 Volume 1: Design and Synthesis © November 2008 Altera Corporation

Instantiating Megafunctions Using the MegaWizard Plug-In Manager

Use the MegaWizard Plug-In Manager as described in this section to create

megafunctions in the Quartus II GUI that you can instantiate in your HDL code. The

MegaWizard Plug-In Manager provides a graphical user interface to customize and

parameterize megafunctions, and ensures that you set all megafunction parameters

properly. When you finish setting parameters, you can specify which files you want to

be generated. Depending on which language you choose, the MegaWizard Plug-In

Manager instantiates the megafunction with the correct parameters and generates a

megafunction variation file (wrapper file) in Verilog HDL (.v), VHDL (.vhd), or

AHDL (.tdf), along with other supporting files.

The MegaWizard Plug-In Manager provides options to create the following files:

■ A sample instantiation template for the language of the variation file

(_inst.v|vhd|tdf).

■ Component Declaration File (.cmp) that can be used in VHDL Design Files

■ ADHL Include File (.inc) that can be used in Text Design Files (.tdf)

■ Quartus II Block Symbol File (.bsf) for schematic designs

■ Verilog HDL module declaration file that can be used when instantiating the

megafunction as a black box in a third-party synthesis tool (_bb.v).

■ If you enable the option to generate a synthesis area and timing estimation netlist,

the MegaWizard Plug-In Manager generates an additional synthesis netlist file

(_syn.v). Refer to “Creating a Netlist File for Other Synthesis Tools” on page 6–5

for details.

Table 6–1 lists and describes the files generated by the MegaWizard Plug-In Manager.

Table 6 –1. MegaWizard Plug-In Manager Generated Files (Part 1 of 2)

File Description

<output file>.v (1) Verilog HDL Variation Wrapper File—Megafunction wrapper file for instantiation in a

Verilog HDL design.

<output file>.vhd (1) VHDL Variation Wrapper File—Megafunction wrapper file for instantiation in a VHDL design.

<output file>.tdf (1) AHDL Variation Wrapper File—Megafunction wrapper file for instantiation in an AHDL design.

<output file>.inc ADHL Include File—Used in AHDL designs.

<output file>.cmp Component Declaration File—Used in VHDL designs.

<output file>.bsf Block Symbol File—Used in Quartus II Block Design Files (.bdf).

<output file>_inst.v Verilog HDL Instantiation Template—Sample Verilog HDL instantiation of the module in the

megafunction wrapper file.

<output file>_inst.vhd VHDL Instantiation Template—Sample VHDL instantiation of the entity in the megafunction

wrapper file.

<output file>_inst.tdf Text Design File Instantiation Template—Sample AHDL instantiation of the subdesign in the

megafunction wrapper file.

<output file>_bb.v Black box Verilog HDL Module Declaration—Hollow-body module declaration that can be

used in Verilog HDL designs to specify port directions when creating black boxes in

third-party synthesis tools.

Chapter 6: Recommended HDL Coding Styles 6–5

Instantiating Altera Megafunctions in HDL Code

Creating a Netlist File for Other Synthesis Tools

When you use certain megafunctions with third-party EDA synthesis tools (that is,

tools other than Quartus II integrated synthesis), you can optionally create a netlist for

area and timing estimation instead of a wrapper file.

The netlist file is a representation of the customized logic used in the Quartus II

software. The file provides the connectivity of architectural elements in the

megafunction but may not represent true functionality. This information enables

certain third-party synthesis tools to better report area and timing estimates. In

addition, synthesis tools can use the timing information to focus timing-driven

optimizations and improve the quality of results.

To generate the netlist, turn on Generate a synthesis area and timing estimation

netlist on the EDA page of the MegaWizard Plug-In Manager. The netlist file is called

<output file>_syn.v. If you use this netlist for synthesis, you must include the

megafunction wrapper file <output file>.v|vhd in your Quartus II project for

placement and routing.

Your synthesis tool may call the Quartus II software in the background to generate

this netlist, so you might not be required to perform the extra step of turning on this

option.

f For information about support for area and timing estimation netlists in your

synthesis tool, refer to the tool vendor’s documentation or the appropriate chapter in

the Synthesis section in volume 1 of the Quartus II Handbook.

Instantiating Megafunctions Using the Port and Parameter Definition

You can instantiate the megafunction directly in your Verilog HDL, VHDL, or AHDL

code by calling the megafunction and setting its parameters as you would any other

module, component, or subdesign.

f Refer to the specific megafunction in the Quartus II Help for a list of the megafunction

ports and parameters. The Quartus II Help also provides a sample VHDL component

declaration and AHDL function prototype for each megafunction.

1 Altera strongly recommends that you use the MegaWizard Plug-In Manager for

complex megafunctions such as PLLs, transceivers, and LVDS drivers. For details

about using the MegaWizard Plug-In Manager, refer to “Instantiating Megafunctions

Using the MegaWizard Plug-In Manager” on page 6–4.

<output file>_syn.v (2) Synthesis area and timing estimation netlist—Megafunction netlist used by certain third-party

synthesis tools to improve area and timing estimations.

Notes to Ta ble 6– 1 :

(1) The MegaWizard Plug-In Manager generates either the Verilog HDL, VHDL, or AHDL Variation Wrapper File, depending on the language you

select for the output file on the megafunction-selection page of the wizard.

(2) The MegaWizard Plug-In Manager generates this file only if you turn on the Generate a synthesis area and timing estimation netlist option

on the EDA page of the wizard.

Table 6 –1. MegaWizard Plug-In Manager Generated Files (Part 2 of 2)

File Description

剩余71页未读，继续阅读

评论收藏

内容反馈

tian_yi8888

粉丝: 0
资源: 5

altera 推荐的代码风格

最新资源

altera 推荐的代码风格

Altera官方的SDRAM模块源代码，VerilogHDL

适合altera的Verilog代码风格

Altera推荐Verilog HDL代码风格

Altera器件的推荐代码风格.pdf

Altera器件的推荐代码风格

Altera器件的推荐代码风格.rar

Altera代码风格讲义

FPGA设计的代码风格

Altera 培训资料第二包.rar

Altera 乘法器 IP核 Modelsim仿真

Verilog Coding Style

Altera公司的Verilog Coding Style

黑金Altera开发板Verilog教程V1.1.pdf

altera 官方资料--verilog 编写规范

FPGA Verilog串口屏控制源码及测试工程，使用Altera FPGA测试。

Altera面向OpenCL的软件开发套件 快速提供原型开发

Using the Altera MAX10 FPGA chip and Intel Quartus-Prime

Altera FPGA_CPLD设计 高级篇

Altera-Recommended-HDL-Coding-Style.rar_coding style_style

Altera FPGA_CPLD设计 高级篇(2)

基于Altera的FPGA的8051核设计

可编程逻辑器件编程技术：Altera Quartus II软件操作基础.pdf

lcd汉字取模软件软件开发.rar

VerilogCodingStyle.pdf

可编程逻辑设计指导原则PPT课件.pptx

很好的Vhdl,Verilog源代码集合，新手必下！

Quartus II 18.0 用户推荐设计指南

Recommended HDL Coding Styles

最新资源

Altera面向OpenCL的软件开发套件快速提供原型开发

Altera FPGA_CPLD设计高级篇

Altera FPGA_CPLD设计高级篇(2)