36
XCell 31 - 1Q99
end process EQUALITY;
end architecture RTL;
module COMPARATOR_A
(AIN1, AIN2, AEQ);
input [7:0] AIN1, AIN2;
output AEQ;
integer I;
reg AEQ;
//Compare each bit in turn in a “for” loop
always@(AIN1 or AIN2)
begin: EQUALITY
AEQ = 1;
for (I=0; I<7; I=I+1)
if (AIN1[I] != AIN2[I])
AEQ=0;
else
;
end
endmodule
Comparator A - Bit by Bit Compare
library IEEE;
use IEEE.STD_LOGIC_1164.all,
IEEE.NUMERIC_STD.all;
entity COMPARATOR_A is
port (AIN1, AIN2: in unsigned(7 downto 0);
AEQ: out std_logic);
end entity COMPARATOR_A;
architecture RTL of COMPARATOR_A is
begin
EQUALITY:process (AIN1, AIN2)
begin
— Compare each bit in turn in a “for” loopp
AEQ <= ‘1’;
for I in 0 to 7 loop
if(AIN1(I) /= AIN2(I)) then
AEQ <= ‘0’;
exit;
else
null;
end if;
end loop;
omparators are best modeled with word-wise com-
pares within a PROCESS or an ALWAYS block that
contains the IF statement and an ELSE clause, and no
ELSE-IF clauses. Conditional signal assignments in VHDL or
conditional continuous assignments in Verilog could be used,
but at a high cost in simulation time. Without the sensitivity list
in VHDL or the event list in Verilog the simulators would
constantly be checking the statements even when the inputs
COLUMN
by Roberta Fulton, Technical
Marketing Engineer, Xilinx,
roberta.fulton@xilinx.com
Creating the Most
Efficient Comparators
C
are unchanging, thus slowing simulation time considerably. If
compared bit-wise some synthesizers may not see optimizations
available to them such as the use of H-MAPs.
Three alternative representations to infer an 8-bit equality
comparator are shown below. The first, COMPARATOR_A does a
bit by bit compare (Figure 1), the second COMPARATOR_B sets
the default first, then compares (Figure 2), so does not have an
ELSE clause, the third has a complete IF-THEN-ELSE statement
(Figure 3).
end architecture RTL;
module COMPARATOR_B
(BIN1, BIN2, BEQ);
input [7:0] BIN1, BIN2;
output BEQ;
integer I;
reg BEQ;
//No “else” is required since default is
defined before the “if”
always@(BIN1 or BIN2)
begin: EQUALITY
BEQ = 0;
if (BIN1 == BIN2)
BEQ=1;
end
endmodule
Comparator B No Else Clause
library IEEE;
use IEEE.STD_LOGIC_1164.all,
IEEE.NUMERIC_STD.all;
entity COMPARATOR_B is
port (BIN1, BIN2: in unsigned(7 downto 0);
BEQ: out std_logic);
end entity COMPARATOR_B;
architecture RTL of COMPARATOR_B is
begin
EQUALITY:process (BIN1, BIN2)
begin
— No “else” is required since default is
defined before the “if””
BEQ <=’0’;
if (BIN1 = BIN2) then
BEQ <= ‘1’;
end if;
end process EQUALITY;
Figure 1
Figure 2
THE XILINX
HDL
ADVISOR
资源评论
超人Roger2018-07-18不错不错，很有参考价值
tanglisan
- 粉丝: 0
- 资源: 3
最新资源
- Cocos2d-x 2.2.1 版本资源
- 关于DeepSeek的几点思考.pdf
- 基于ISODATA算法优化的负荷场景曲线聚类方法（包含K-means、L-ISODATA及K-L-ISODATA算法，聚类效果评价与风光场景应用）,基于ISODATA改进算法的负荷场景曲线聚类：多方法
- qpress的二进制命令
- 基于Matlab Simulink的风光储并网双闭环控制策略及单极调制协同运行模型研究,基于Matlab Simulink的风光储并网双闭环控制策略及其单极调制协同运行模型研究,风光储并网协同运行模型
- deepseek详细对话
- 遗传算法与动态窗口法DWA融合优化：全局路径规划与动态环境适应的算法创新,遗传算法优化与动态窗口法融合：全局最优路径规划与动态环境适应策略,遗传算法（GA）优化与动态窗口法dwa融合，效果极佳，算法新
- COMSOL仿真揭示变压器磁致伸缩现象：电路磁场分布、振动噪声及受力和噪声分布研究,COMSOL仿真揭示变压器磁致伸缩机理：电路磁场分布、振动数据与噪声分布综合分析,COMSOL仿真，变压器磁致伸缩
- 数据科学相关人员的岗位及薪资数据.zip
- 零基础入门转录组下游分析-机器学习算法之xgboost（筛选特征基因）教程配套资源
- 基于相量模型的UPFC在500kV与230kV输电系统中的功率流控仿真研究,基于相量模型的UPFC在500kV与230kV输电系统中的功率流控仿真研究,UPFC（相量模型）控制500 kV 230
- 中秋节静态网站网页设计（HTML+CSS+JS）期末大作业.zip
- C#开发TCP通信demo
- 基于Electron+HTML+CSS+Node.js开发的的中国象棋游戏,支持人机对大模型AI对战 （源码）
- 基于粒子群算法的地表水源热泵系统建模与最佳制冷制热量求解研究,水源热泵系统建模与粒子群优化：求解热泵机组最佳制冷制热量算法研究,matlab代码 从水源热泵机组角度对地表水源热泵系统建模，并采用粒子群
- COCOS2DX 2.2.2 引擎下载
资源上传下载、课程学习等过程中有任何疑问或建议，欢迎提出宝贵意见哦~我们会及时处理！
点击此处反馈
