36
XCell 31 - 1Q99
end process EQUALITY;
end architecture RTL;
module COMPARATOR_A
(AIN1, AIN2, AEQ);
input [7:0] AIN1, AIN2;
output AEQ;
integer I;
reg AEQ;
//Compare each bit in turn in a “for” loop
always@(AIN1 or AIN2)
begin: EQUALITY
AEQ = 1;
for (I=0; I<7; I=I+1)
if (AIN1[I] != AIN2[I])
AEQ=0;
else
;
end
endmodule
Comparator A - Bit by Bit Compare
library IEEE;
use IEEE.STD_LOGIC_1164.all,
IEEE.NUMERIC_STD.all;
entity COMPARATOR_A is
port (AIN1, AIN2: in unsigned(7 downto 0);
AEQ: out std_logic);
end entity COMPARATOR_A;
architecture RTL of COMPARATOR_A is
begin
EQUALITY:process (AIN1, AIN2)
begin
— Compare each bit in turn in a “for” loopp
AEQ <= ‘1’;
for I in 0 to 7 loop
if(AIN1(I) /= AIN2(I)) then
AEQ <= ‘0’;
exit;
else
null;
end if;
end loop;
omparators are best modeled with word-wise com-
pares within a PROCESS or an ALWAYS block that
contains the IF statement and an ELSE clause, and no
ELSE-IF clauses. Conditional signal assignments in VHDL or
conditional continuous assignments in Verilog could be used,
but at a high cost in simulation time. Without the sensitivity list
in VHDL or the event list in Verilog the simulators would
constantly be checking the statements even when the inputs
COLUMN
by Roberta Fulton, Technical
Marketing Engineer, Xilinx,
roberta.fulton@xilinx.com
Creating the Most
Efficient Comparators
C
are unchanging, thus slowing simulation time considerably. If
compared bit-wise some synthesizers may not see optimizations
available to them such as the use of H-MAPs.
Three alternative representations to infer an 8-bit equality
comparator are shown below. The first, COMPARATOR_A does a
bit by bit compare (Figure 1), the second COMPARATOR_B sets
the default first, then compares (Figure 2), so does not have an
ELSE clause, the third has a complete IF-THEN-ELSE statement
(Figure 3).
end architecture RTL;
module COMPARATOR_B
(BIN1, BIN2, BEQ);
input [7:0] BIN1, BIN2;
output BEQ;
integer I;
reg BEQ;
//No “else” is required since default is
defined before the “if”
always@(BIN1 or BIN2)
begin: EQUALITY
BEQ = 0;
if (BIN1 == BIN2)
BEQ=1;
end
endmodule
Comparator B No Else Clause
library IEEE;
use IEEE.STD_LOGIC_1164.all,
IEEE.NUMERIC_STD.all;
entity COMPARATOR_B is
port (BIN1, BIN2: in unsigned(7 downto 0);
BEQ: out std_logic);
end entity COMPARATOR_B;
architecture RTL of COMPARATOR_B is
begin
EQUALITY:process (BIN1, BIN2)
begin
— No “else” is required since default is
defined before the “if””
BEQ <=’0’;
if (BIN1 = BIN2) then
BEQ <= ‘1’;
end if;
end process EQUALITY;
Figure 1
Figure 2
THE XILINX
HDL
ADVISOR
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超人Roger2018-07-18不错不错，很有参考价值
