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OCP NIC 3.0 Design Specification
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OCP 规范 电气规范，OCP NIC 3.0 Design Specification
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OCP NIC 3.0 Design Specification
Version 1.1.0
Author: OCP Server Workgroup, OCP NIC subgroup
Open Compute Project OCP NIC 3.0
Version 1.1.0
http://opencompute.org 2
Table of Contents
1 Overview ..........................................................................................................................................................................10
1.1 License ......................................................................................................................................................................... 10
1.2 Acknowledgements ..................................................................................................................................................... 11
1.3 References ................................................................................................................................................................... 12
1.3.1 Trademarks ........................................................................................................................................................ 13
1.4 Acronyms ..................................................................................................................................................................... 14
1.5 Conventions ................................................................................................................................................................. 15
1.6 Background .................................................................................................................................................................. 16
1.7 Overview ...................................................................................................................................................................... 18
1.7.1 Mechanical Form Factor Overview .................................................................................................................... 18
1.7.2 Electrical Overview ............................................................................................................................................ 20
1.7.2.1 Primary Connector ................................................................................................................................... 20
1.7.2.2 Secondary Connector ............................................................................................................................... 21
1.8 Non-NIC Use Cases ....................................................................................................................................................... 21
2 Mechanical Card Form Factor ...........................................................................................................................................22
2.1 Form Factor Options .................................................................................................................................................... 22
2.1.1 SFF Faceplate Configurations ............................................................................................................................. 24
2.1.2 LFF Faceplate Configurations ............................................................................................................................. 28
2.2 Line Side I/O Implementations .................................................................................................................................... 32
2.3 Top Level Assembly (SFF and LFF) ................................................................................................................................ 33
2.4 Faceplate Subassembly (SFF and LFF) .......................................................................................................................... 34
2.4.1 Faceplate Subassembly – Exploded View .......................................................................................................... 34
2.4.2 Faceplate Subassembly – Bill of Materials (BOM).............................................................................................. 34
2.4.3 SFF Generic I/O Faceplate .................................................................................................................................. 37
2.4.4 LFF Generic I/O Faceplate .................................................................................................................................. 38
2.4.5 Ejector Lever (SFF) ............................................................................................................................................. 39
2.4.6 Ejector Levers (LFF) ............................................................................................................................................ 40
2.4.7 Ejector Lock (SFF and LFF) .................................................................................................................................. 41
2.4.8 Clinch Nut (SFF and LFF) ..................................................................................................................................... 42
2.5 Card Keep Out Zones ................................................................................................................................................... 43
2.5.1 SFF Keep Out Zones ........................................................................................................................................... 43
2.5.2 LFF Keep Out Zones ........................................................................................................................................... 46
2.6 Baseboard Keep Out Zones .......................................................................................................................................... 49
2.7 Insulation Requirements .............................................................................................................................................. 50
2.7.1 SFF Insulator ...................................................................................................................................................... 50
2.7.2 LFF Insulator ....................................................................................................................................................... 52
2.8 Critical-to-Function (CTF) Dimensions (SFF and LFF) .................................................................................................... 55
2.8.1 CTF Tolerances ................................................................................................................................................... 55
2.8.2 SFF Pull Tab CTF Dimensions .............................................................................................................................. 55
2.8.3 SFF Ejector Latch CTF Dimensions ...................................................................................................................... 57
2.8.4 SFF Internal Lock CTF Dimensions ...................................................................................................................... 58
2.8.5 SFF Baseboard CTF Dimensions ......................................................................................................................... 59
2.8.6 LFF Ejector Latch CTF Dimensions ...................................................................................................................... 62
2.8.7 LFF Baseboard CTF Dimensions ......................................................................................................................... 63
2.9 Labeling Requirements ................................................................................................................................................ 66
2.9.1 General Guidelines for Label Contents .............................................................................................................. 66
2.9.2 MAC Address Labeling Requirements ................................................................................................................ 67
2.9.2.1 MAC Address Label Example 1 – Quad Port with Single Host, Single Managed Controller ...................... 68
2.9.2.2 MAC Address Label Example 2 – Octal Port with Single Host, Dual Managed Controllers ....................... 68
2.9.2.3 MAC Address Label Example 3 – Quad Port with Dual Hosts, Dual Managed Controllers ....................... 69
2.9.2.4 MAC Address Label Example 4 – Singe Port with Quad Host, Single Managed Controller ....................... 69
2.10 Mechanical CAD Package Examples ............................................................................................................................. 71
3 Electrical Interface Definition – Card Edge and Baseboard ................................................................................................72
3.1 Card Edge Gold Finger Requirements .......................................................................................................................... 72
3.1.1 Gold Finger Mating Sequence ............................................................................................................................ 74
3.2 Baseboard Connector Requirements ........................................................................................................................... 78
3.2.1 Right Angle Connector ....................................................................................................................................... 78
Open Compute Project OCP NIC 3.0
Version 1.1.0
http://opencompute.org 3
3.2.2 Right Angle Offset .............................................................................................................................................. 79
3.2.3 Straddle Mount Connector ................................................................................................................................ 79
3.2.4 Straddle Mount Offset and PCB Thickness Options ........................................................................................... 81
3.2.5 LFF Connector Locations .................................................................................................................................... 82
3.3 Pin Definition ............................................................................................................................................................... 82
3.3.1 Primary Connector ............................................................................................................................................. 83
3.3.2 Secondary Connector ......................................................................................................................................... 85
3.4 Signal Descriptions ....................................................................................................................................................... 86
3.4.1 PCIe Interface Pins ............................................................................................................................................. 86
3.4.2 PCIe Present and Bifurcation Control Pins ......................................................................................................... 92
3.4.3 SMBus Interface Pins ......................................................................................................................................... 95
3.4.4 NC-SI over RBT Interface Pins ............................................................................................................................ 96
3.4.5 Scan Chain Pins ................................................................................................................................................ 104
3.4.6 Power Supply Pins ............................................................................................................................................ 113
3.4.7 USB 2.0 (A68/A69) – Primary Connector Only ................................................................................................. 118
3.4.8 UART (A68/A69) – Secondary Connector Only ................................................................................................ 120
3.4.9 RFU[1:4] Pins .................................................................................................................................................... 122
3.5 PCIe Bifurcation Mechanism ...................................................................................................................................... 123
3.5.1 PCIe OCP NIC 3.0 Card to Baseboard Bifurcation Configuration (PRSNTA#, PRSNTB[3:0]#) ............................ 123
3.5.2 PCIe Baseboard to OCP NIC 3.0 Card Bifurcation Configuration (BIF[2:0]#) .................................................... 123
3.5.3 PCIe Bifurcation Decoder ................................................................................................................................. 124
3.5.4 Bifurcation Detection Flow .............................................................................................................................. 126
3.5.5 PCIe Bifurcation Examples ............................................................................................................................... 127
3.5.5.1 Single Host (1 x16) Baseboard with a 1 x16 OCP NIC 3.0 Card (Single Controller) ................................. 127
3.5.5.2 Single Host (2 x8) Baseboard with a 2 x8 OCP NIC 3.0 Card (Dual Controllers) ...................................... 128
3.5.5.3 Quad Host (4 x4) Baseboard with a 4 x4 OCP NIC 3.0 Card (Single Controller) ...................................... 129
3.5.5.4 Quad Host (4 x4) Baseboard with a 4 x4 OCP NIC 3.0 Card (Quad Controllers) ..................................... 130
3.5.5.5 Single Host (1 x16, no Bifurcation) Baseboard with a 2 x8 OCP NIC 3.0 Card (Dual Controller) ............. 131
3.6 PCIe REFCLK and PERST# Mapping............................................................................................................................. 132
3.6.1 SFF PCIe REFCLK and PERST# Mapping ............................................................................................................ 133
3.6.2 LFF PCIe REFCLK and PERST# Mapping ............................................................................................................ 136
3.6.3 REFCLK and PERST# Mapping Expansion ......................................................................................................... 138
3.7 Port Numbering and LED Implementations ............................................................................................................... 139
3.7.1 OCP NIC 3.0 Port Naming and Port Numbering ............................................................................................... 139
3.7.2 OCP NIC 3.0 Card LED Configuration ................................................................................................................ 139
3.7.3 OCP NIC 3.0 Card LED Ordering ....................................................................................................................... 141
3.7.4 Baseboard LEDs Configuration over the Scan Chain ........................................................................................ 142
3.8 Power State Machine ................................................................................................................................................. 144
3.8.1 NIC Power Off .................................................................................................................................................. 145
3.8.2 ID Mode ........................................................................................................................................................... 145
3.8.3 Aux Power Mode ............................................................................................................................................. 146
3.8.4 Main Power Mode ........................................................................................................................................... 146
3.8.5 Programming Mode ......................................................................................................................................... 146
3.9 Power Supply Rail Requirements and Slot Power Envelopes ..................................................................................... 147
3.10 Hot Swap Considerations for +12V_EDGE and +3.3V_EDGE Rails ............................................................................. 148
3.11 Power Sequence Timing Requirements ..................................................................................................................... 149
3.12 Digital I/O Specifications ............................................................................................................................................ 153
4 Management and Pre-OS Requirements ......................................................................................................................... 154
4.1 Sideband Management Interface and Transport ....................................................................................................... 154
4.2 NC-SI Traffic ............................................................................................................................................................... 155
4.3 Management Controller (MC) MAC Address Provisioning ......................................................................................... 155
4.4 ASIC Die Temperature Reporting ............................................................................................................................... 157
4.5 Power Consumption Reporting .................................................................................................................................. 160
4.6 Pluggable Transceiver Module Status and Temperature Reporting .......................................................................... 161
4.7 Management and Pre-OS Firmware Inventory and Update ...................................................................................... 161
4.7.1 Secure Firmware .............................................................................................................................................. 161
4.7.2 Firmware Inventory ......................................................................................................................................... 162
4.7.3 Firmware Inventory and Update in Multi-Host Environments......................................................................... 162
Open Compute Project OCP NIC 3.0
Version 1.1.0
http://opencompute.org 4
4.8 NC-SI Package Addressing and Hardware Arbitration Requirements ........................................................................ 163
4.8.1 NC-SI over RBT Package Addressing................................................................................................................. 163
4.8.2 Arbitration Ring Connections ........................................................................................................................... 163
4.9 SMBus 2.0 Addressing Requirements ........................................................................................................................ 163
4.9.1 SMBus Address Map ........................................................................................................................................ 164
4.10 FRU EEPROM .............................................................................................................................................................. 164
4.10.1 FRU EEPROM Addressing and Size ................................................................................................................... 164
4.10.2 FRU EEPROM Write Protection ........................................................................................................................ 166
4.10.3 FRU EEPROM Content Requirements .............................................................................................................. 166
4.10.4 FRU Template .................................................................................................................................................. 173
5 Routing Guidelines and Signal Integrity Considerations .................................................................................................. 174
5.1 NC-SI over RBT ........................................................................................................................................................... 174
5.1.1 SFF Baseboard Requirements .......................................................................................................................... 175
5.1.2 LFF Baseboard Requirements .......................................................................................................................... 176
5.1.3 SFF OCP NIC 3.0 Card Requirements ................................................................................................................ 176
5.1.4 LFF OCP NIC 3.0 Card Requirements ................................................................................................................ 177
5.2 SMBus 2.0 .................................................................................................................................................................. 177
5.3 PCIe ............................................................................................................................................................................ 178
5.3.1 Channel Requirements .................................................................................................................................... 178
5.3.1.1 REFCLK requirements ............................................................................................................................. 178
5.3.1.2 Add-in Card Electrical Budgets ............................................................................................................... 178
5.3.1.3 Baseboard Channel Budget .................................................................................................................... 179
5.3.1.4 SFF-TA-1002 Connector Channel Budget ............................................................................................... 179
5.3.1.5 Differential Impedance (Informative) .................................................................................................... 179
5.3.2 Test Fixtures ..................................................................................................................................................... 179
5.3.2.1 Compliance Load Board (CLB) ................................................................................................................ 180
5.3.2.2 Compliance Baseboard (CBB) ................................................................................................................. 181
5.3.3 Test Methodology ............................................................................................................................................ 181
5.3.3.1 Test Setup .............................................................................................................................................. 181
6 Thermal and Environmental ........................................................................................................................................... 183
6.1 Airflow Direction ........................................................................................................................................................ 183
6.1.1 Hot Aisle Cooling .............................................................................................................................................. 183
6.1.2 Cold Aisle Cooling ............................................................................................................................................ 184
6.2 Thermal Design Guidelines ........................................................................................................................................ 185
6.2.1 SFF Card ASIC Cooling – Hot Aisle .................................................................................................................... 185
6.2.2 LFF Card ASIC Cooling – Hot Aisle .................................................................................................................... 189
6.2.3 SFF Card ASIC Cooling – Cold Aisle ................................................................................................................... 191
6.2.4 LFF Card ASIC Cooling – Cold Aisle ................................................................................................................... 194
6.3 Thermal Simulation (CFD) Modeling .......................................................................................................................... 196
6.4 Thermal Test Fixture .................................................................................................................................................. 196
6.4.1 Test Fixture for SFF Card .................................................................................................................................. 197
6.4.2 Test Fixture for LFF Card .................................................................................................................................. 199
6.4.3 Test Fixture Airflow Direction .......................................................................................................................... 201
6.4.4 Thermal Test Fixture Candlestick Sensors........................................................................................................ 201
6.5 Card Sensor Requirements ........................................................................................................................................ 204
6.6 Card Cooling Tiers ...................................................................................................................................................... 204
6.7 Non-Operational Shock & Vibration Testing .............................................................................................................. 206
6.7.1 Shock & Vibe Test Fixture ................................................................................................................................ 206
6.7.2 Test Procedure ................................................................................................................................................. 207
6.8 Dye and Pull Test Method .......................................................................................................................................... 209
6.9 Gold Finger Plating Requirements ............................................................................................................................. 211
6.9.1 Host Side Gold Finger Plating Requirements ................................................................................................... 211
6.9.2 Line Side Gold Finger Durability Requirements ............................................................................................... 211
7 Regulatory...................................................................................................................................................................... 212
7.1 Required Compliance ................................................................................................................................................. 212
7.1.1 Required Environmental Compliance .............................................................................................................. 212
7.1.2 Required EMC Compliance .............................................................................................................................. 212
7.1.3 Required Product Safety Compliance .............................................................................................................. 213
Open Compute Project OCP NIC 3.0
Version 1.1.0
http://opencompute.org 5
7.1.4 Required Immunity (ESD) Compliance ............................................................................................................. 213
7.2 Recommended Compliance ....................................................................................................................................... 214
7.2.1 Recommended Environmental Compliance..................................................................................................... 214
7.2.2 Recommended EMC Compliance ..................................................................................................................... 214
8 Revision History ............................................................................................................................................................. 215
8.1 Document Revision History ........................................................................................................................................ 215
8.2 FRU Content Revision History .................................................................................................................................... 223
List of Figures
Figure 1: Representative SFF OCP NIC 3.0 Card with Dual QSFP Ports ........................................................................................... 16
Figure 2: Representative LFF OCP NIC 3.0 Card with Dual QSFP Ports and on-board DRAM .......................................................... 17
Figure 3: SFF and LFF Block Diagrams (not to scale) ....................................................................................................................... 18
Figure 4: Primary Connector (4C+) and Secondary Connector (4C) (LFF) OCP NIC 3.0 Cards ......................................................... 22
Figure 5: Primary Connector (4C+) Only (LFF) OCP NIC 3.0 Cards ................................................................................................... 23
Figure 6: Primary Connector (4C+) with 4C and 2C (SFF) OCP NIC 3.0 Cards .................................................................................. 23
Figure 7: SFF NIC Configuration Views ............................................................................................................................................ 25
Figure 8: SFF NIC Line Side 3D Views .............................................................................................................................................. 26
Figure 9: SFF NIC Chassis Mounted 3D Views ................................................................................................................................. 27
Figure 10: LFF NIC Configuration Views .......................................................................................................................................... 29
Figure 11: LFF NIC Line Side 3D Views ............................................................................................................................................ 30
Figure 12: LFF NIC Chassis Mounted 3D Views ............................................................................................................................... 31
Figure 13: PBA Exploded Views (SFF and LFF) ................................................................................................................................. 33
Figure 14: Faceplate Assembly Exploded Views (SFF and LFF) ........................................................................................................ 34
Figure 15: SFF Generic I/O Faceplate with Pulltab Version (2D View) ............................................................................................ 37
Figure 16: SFF Generic I/O Faceplate – Ejector Version (2D View) ................................................................................................. 37
Figure 17: SFF Generic I/O Faceplate – Internal Lock Version (2D View) ........................................................................................ 38
Figure 18: LFF Generic I/O Faceplate – Ejector Version (2D View) ................................................................................................. 38
Figure 19: SFF I/O Faceplate – Ejector Lever (2D View) .................................................................................................................. 39
Figure 20: LFF I/O Faceplate – Ejector Lever (2D View) .................................................................................................................. 40
Figure 21: Ejector Lock .................................................................................................................................................................... 41
Figure 22: Clinch Nut Option A ....................................................................................................................................................... 42
Figure 23: Clinch Nut Option B........................................................................................................................................................ 42
Figure 24: SFF Keep Out Zone – Top View ...................................................................................................................................... 43
Figure 25: SFF Keep Out Zone – Top View – Detail A ...................................................................................................................... 44
Figure 26: SFF Keep Out Zone – Bottom View ................................................................................................................................ 44
Figure 27: SFF Keep Out Zone – Side View ...................................................................................................................................... 45
Figure 28: SFF Keep Out Zone – Side View – Detail D ..................................................................................................................... 45
Figure 29: LFF Keep Out Zone – Top View ...................................................................................................................................... 46
Figure 30: LFF Keep Out Zone – Top View – Detail A ...................................................................................................................... 47
Figure 31: LFF Keep Out Zone – Bottom View ................................................................................................................................ 48
Figure 32: LFF Keep Out Zone – Side View ...................................................................................................................................... 48
Figure 33: LFF Keep Out Zone – Side View – Detail D ..................................................................................................................... 49
Figure 34: SFF Bottom Side Insulator (3D View) ............................................................................................................................. 50
Figure 35: SFF Bottom Side Insulator (Top and Side View) ............................................................................................................. 51
Figure 36: SFF Bottom Side Insulator (alternate) (Top and Side View) ........................................................................................... 52
Figure 37: LFF Bottom Side Insulator (3D View) ............................................................................................................................. 52
Figure 38: LFF Bottom Side Insulator (Top and Side View) ............................................................................................................. 53
Figure 39: LFF Bottom Side Insulator (alternate) (Top and Side View) ........................................................................................... 54
Figure 40: SFF OCP NIC 3.0 Card with Pull Tab CTF Dimensions (Top View) ................................................................................... 55
Figure 41: SFF OCP NIC 3.0 Card with Pull Tab CTF Dimensions (Front View) ................................................................................. 56
Figure 42: SFF OCP NIC 3.0 Card with Pull Tab CTF Dimensions (Side View) .................................................................................. 56
Figure 43: SFF OCP NIC 3.0 Card with Ejector CTF Dimensions (Top View) ..................................................................................... 57
Figure 44: SFF OCP NIC 3.0 Card with Ejector CTF Dimensions (Front View) .................................................................................. 57
Figure 45: SFF OCP NIC 3.0 Card with Ejector CTF Dimensions (Side View) .................................................................................... 58
Figure 46: SFF OCP NIC 3.0 Card with Internal Lock CTF Dimensions (Top View) ........................................................................... 58
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