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<title>Zynq UltraScale+ MPSoC PS configuration detail</title>
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<script type="text/javascript" language="JavaScript">function ChangeSilRegLink(id) { var ver=document.getElementById(id).value; if (ver == "Silicon3.0") { document.getElementById("MIO_Registers").href="#psu_mio_init_data_3_0"; document.getElementById("PLL_Registers").href="#psu_pll_init_data_3_0"; document.getElementById("Clock_Registers").href="#psu_clock_init_data_3_0"; document.getElementById("DDR_Registers").href="#psu_ddr_init_data_3_0"; document.getElementById("Peri_Registers").href="#psu_peripherals_init_data_3_0"; window.location = '#psu_mio_init_data_3_0'; } else if (ver == "Silicon2.0") { document.getElementById("MIO_Registers").href="#psu_mio_init_data_2_0"; document.getElementById("PLL_Registers").href="#psu_pll_init_data_2_0"; document.getElementById("Clock_Registers").href="#psu_clock_init_data_2_0"; document.getElementById("DDR_Registers").href="#psu_ddr_init_data_2_0"; document.getElementById("Peri_Registers").href="#psu_peripherals_init_data_2_0"; window.location = '#psu_mio_init_data_2_0'; } else { document.getElementById("MIO_Registers").href="#psu_mio_init_data_1_0"; document.getElementById("PLL_Registers").href="#psu_pll_init_data_1_0"; document.getElementById("Clock_Registers").href="#psu_clock_init_data_1_0"; document.getElementById("DDR_Registers").href="#psu_ddr_init_data_1_0"; document.getElementById("Peri_Registers").href="#psu_peripherals_init_data_1_0"; window.location = '#psu_mio_init_data_1_0'; }}</script>
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<DIV class="navlink">Zynq UltraScale+ PS Summary Viewer
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<DIV class="sitename">Zynq UltraScale+ Summary Report
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<DIV class="viewButtons">User Configurations
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<DIV class="viewButton button1">CLK Configurations
</DIV>
</A>
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<A id="DDR_Configurations" href="#DDRInfoTab" style="text-decoration:none">
<DIV class="viewButton button1">DDR Configurations
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</A>
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<A id="GT_Configurations" href="#GTInfoTab" style="text-decoration:none">
<DIV class="viewButton button1">GT Configurations
</DIV>
</A>
</DIV>
<DIV class="content_container">This design is targeted for xczu4ev board (part number: xczu4ev-sfvc784-2-i)
<br>
<H2><a name="summTAB">Zynq UltraScale+ Design Summary</a></H2>
<TABLE border=1 cellspacing=0 BORDERCOLOR=black WIDTH=100%">
<TR valign="top">
<TD width=20% BGCOLOR=#C0C0FF>
<B>Device</B>
</TD>
<TD width=80% BGCOLOR=#E6E6E6>
xczu4ev
</TD>
</TR>
<TR valign="top">
<TD width=20% BGCOLOR=#C0C0FF>
<B>SpeedGrade</B>
</TD>
<TD width=80% BGCOLOR=#E6E6E6>
-2
</TD>
</TR>
<TR valign="top">
<TD width=20% BGCOLOR=#C0C0FF>
<B>Part</B>
</TD>
<TD width=80% BGCOLOR=#E6E6E6>
xczu4ev-sfvc784-2-i
</TD>
</TR>
<TR valign="top">
<TD width=20% BGCOLOR=#C0C0FF>
<B>Description</B>
</TD>
<TD width=80% BGCOLOR=#E6E6E6>
Zynq UltraScale+ PS Configuration Re
MPSOC 4EV vivado VCU H264解码 HDMI 输出工程
需积分: 5 92 浏览量
2024-04-08
21:44:08
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MPSOC 4EV vivado VCU H264解码 HDMI 输出工程 （168个子文件） 
zu402_hdmitx.bd 236KB bd_28e6.bd 28KB zu402_hdmitx.bda 28KB zu402_hdmitx.bxml 608B bd_28e6.bxml 603B zu402_hdmitx_v_frmbuf_rd_0_0_MEMORY2LIVE_rom.dat 81B zu402_hdmitx_v_frmbuf_rd_0_0_BYTES_PER_PIXEL_rom.dat 81B zu402_hdmitx_v_frmbuf_rd_0_0_MEMORY2LIVE_rom.dat 81B zu402_hdmitx_v_frmbuf_rd_0_0_BYTES_PER_PIXEL_rom.dat 81B zu402_hdmitx_v_frmbuf_rd_0_0_MultiPixStream2AXIvideo_mapComp_rom.dat 49B zu402_hdmitx_v_frmbuf_rd_0_0_MultiPixStream2AXIvideo_mapComp_rom.dat 49B
psu_init.html 50KB vivado_3109.backup.jou 13KB vivado_3284.backup.jou 9KB vivado_14826.backup.jou 4KB vivado_2067.backup.jou 996B vivado.jou 814B vivado_14505.backup.jou 671B vivado_3109.backup.log 291KB vivado_14826.backup.log 94KB vivado_3284.backup.log 74KB vivado_2067.backup.log 5KB vivado.log 5KB vivado_14505.backup.log 1KB zu402_hdmitx.lpr 284B vivado_pid7781.str 72KB bd_automation_gt.tcl 4KB bd_automation_ss.tcl 2KB bd_70307d20.ui 8KB zu402_hdmitx_v_frmbuf_rd_0_0_Bytes2MultiPixStream.v 164KB zu402_hdmitx_v_frmbuf_rd_0_0_mm_video_m_axi.v 93KB zu402_hdmitx_v_frmbuf_rd_0_0_AXIMMvideo2Bytes4.v 72KB zu402_hdmitx_v_mix_0_0_AXIMMvideo2Bytes_1_s.v 43KB zu402_hdmitx_v_frmbuf_rd_0_0_v_frmbuf_rd.v 34KB zu402_hdmitx_v_mix_0_0_VMixHlsDataFlowFunction_entry193.v 31KB zu402_hdmitx_v_frmbuf_rd_0_0_MultiPixStream2AXIvideo.v 30KB zu402_hdmitx_v_frmbuf_rd_0_0_FrmbufRdHlsDataFlow.v 27KB zu402_hdmitx_v_mix_0_0_Bytes2MultiPixStream_10_s.v 19KB zu402_hdmitx_v_mix_0_0_v_mix_420_to_422_false_4.v 17KB zu402_hdmitx_v_mix_0_0_v_mix_422_to_444_false_5.v 17KB zu402_hdmitx_v_frmbuf_rd_0_0_CTRL_s_axi.v 15KB zu402_hdmitx_v_mix_0_0_v_mix_yuv2rgb_false_6.v 13KB zu402_hdmitx_v_frmbuf_rd_0_0_regslice_both.v 7KB bd_28e6_wrapper.v 7KB zu402_hdmitx_v_frmbuf_rd_0_0_urem_12ns_3ns_2_16_seq_1.v 5KB zu402_hdmitx_v_frmbuf_rd_0_0_fifo_w128_d480_B.v 4KB zu402_hdmitx_wrapper.v 4KB zu402_hdmitx_v_frmbuf_rd_0_0_start_for_MultiPixStream2AXIvideo_U0.v 3KB zu402_hdmitx_v_frmbuf_rd_0_0_start_for_Bytes2MultiPixStream_U0.v 3KB zu402_hdmitx_v_mix_0_0_start_for_v_mix_422_to_444_false_5_U0.v 3KB zu402_hdmitx_v_mix_0_0_start_for_v_mix_420_to_422_false_4_U0.v 3KB zu402_hdmitx_v_mix_0_0_start_for_Bytes2MultiPixStream_10_U0.v 3KB zu402_hdmitx_v_mix_0_0_start_for_v_mix_yuv2rgb_false_6_U0.v 3KB zu402_hdmitx_v_frmbuf_rd_0_0_fifo_w12_d2_S.v 3KB zu402_hdmitx_v_frmbuf_rd_0_0_fifo_w48_d2_S.v 3KB zu402_hdmitx_v_frmbuf_rd_0_0_fifo_w15_d2_S.v 3KB zu402_hdmitx_v_frmbuf_rd_0_0_fifo_w6_d2_S.v 3KB zu402_hdmitx_v_frmbuf_rd_0_0_fifo_w2_d3_S.v 3KB zu402_hdmitx_v_mix_0_0_fifo_w128_d2_S.v 3KB zu402_hdmitx_v_mix_0_0_fifo_w12_d4_S.v 3KB zu402_hdmitx_v_frmbuf_rd_0_0_hls_deadlock_detection_unit.v 3KB zu402_hdmitx_v_frmbuf_rd_0_0_mux_63_8_1_1.v 2KB zu402_hdmitx_v_frmbuf_rd_0_0_MultiPixStream2AXIvideo_mapComp.v 1KB zu402_hdmitx_v_frmbuf_rd_0_0_BYTES_PER_PIXEL.v 1KB zu402_hdmitx_v_frmbuf_rd_0_0_MEMORY2LIVE.v 1KB zu402_hdmitx_v_frmbuf_rd_0_0_mul_mul_12ns_12ns_24_4_1.v 1KB zu402_hdmitx_v_frmbuf_rd_0_0_mul_mul_12ns_14ns_25_4_1.v 1KB zu402_hdmitx_v_mix_0_0_mul_mul_16ns_16ns_32_4_1.v 1KB zu402_hdmitx_v_frmbuf_rd_0_0_reg_unsigned_short_s.v 1KB zu402_hdmitx_v_frmbuf_rd_0_0_mul_12ns_3ns_15_1_1.v 1KB zu402_hdmitx_v_frmbuf_rd_0_0_hls_deadlock_report_unit.vh 40KB zu402_hdmitx_v_frmbuf_rd_0_0_hls_deadlock_detector.vh 13KB gui_handlers.wdf 802B java_command_handlers.wdf 517B zu402_hdmitx_zynq_ultra_ps_e_0_0.xci 722KB zu402_hdmitx_xbar_3.xci 560KB zu402_hdmitx_xbar_4.xci 548KB zu402_hdmitx_xbar_1.xci 522KB zu402_hdmitx_xbar_2.xci 522KB bd_28e6_axi_crossbar_0.xci 498KB zu402_hdmitx_v_mix_0_0.xci 264KB zu402_hdmitx_vcu_0_0.xci 217KB zu402_hdmitx_vid_phy_controller_0_gtwrapper.xci 192KB zu402_hdmitx_vid_phy_controller_0.xci 177KB bd_28e6_v_hdmi_tx_0.xci 121KB zu402_hdmitx_v_hdmi_tx_ss_0_0.xci 101KB zu402_hdmitx_clk_wiz_0_0.xci 100KB zu402_hdmitx_s01_regslice_32.xci 83KB zu402_hdmitx_s00_regslice_33.xci 83KB zu402_hdmitx_s01_regslice_33.xci 83KB zu402_hdmitx_s00_regslice_32.xci 83KB zu402_hdmitx_m00_regslice_33.xci 83KB zu402_hdmitx_m00_regslice_32.xci 83KB zu402_hdmitx_auto_cc_4.xci 81KB zu402_hdmitx_v_frmbuf_rd_0_0.xci 80KB zu402_hdmitx_auto_us_0.xci 73KB zu402_hdmitx_auto_ds_0.xci 72KB zu402_hdmitx_auto_pc_0.xci 65KB zu402_hdmitx_auto_cc_2.xci 64KB zu402_hdmitx_auto_cc_1.xci 64KB共 168 条
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