DMA Subsystem for PCIe v2.0 www.xilinx.com 4
PG195 June 8, 2016 Product Specification
Introduction
The Xilinx® DMA Subsystem for PCI Express®
(PCIe™) implements a high performance,
configurable Scatter Gather DMA for use with
the PCI Express® 3.x Integrated Block. The IP
provides an optional AXI4 or AXI4-Stream user
interface.
Features
• Supports UltraScale™ architecture and
Virtex®-7 XT FPGA Gen3 Integrated
(Endpoint only) Blocks for PCI Express
• Support for 64, 128, and 256-bit datapath
width matching the PCI Express Integrated
Block interface datapath width
• 64-bit source, destination, and descriptor
address
• Up to four host-to-card (H2C/Read) data
channels
• Up to four card-to-host (C2H/Write) data
channels
• Configurable user interface - Common AXI4
memory mapped (MM) user interface or a
separate AXI4-Stream user interface
• Compliant with AXI4, AXI4-Lite, and
AXI4-Stream protocols
• AXI4 MM Master DMA host or peer initiated
bypass interface for high bandwidth access
to user logic
• Host configuration access to user logic
through an AXI4-Lite Master interface
• IP internal configuration and status
registers access to user logic through an
AXI4-Lite Slave interface
• Scatter Gather descriptor list supporting
unlimited list size
• 28-bit max transfer length per descriptor
• Legacy, MSI, and MSI-X interrupts
• Block fetches of contiguous descriptors
•Poll Mode
• Descriptor Bypass interface
• Arbitrary source and destination address
• Linux driver available (see AR 65444
)
Dr
IP Facts
IP Facts Table
Core Specifics
Supported
Device Family
(1)
UltraScale Architecture,
Virtex-7 XT
Supported User
Interfaces
AXI4, AXI4-Lite, AXI4-Stream
Resources Performance and Resource Utilization web page
Provided with Core
Design Files Encrypted System Verilog
Example Design Verilog
Test Bench Verilog
Constraints File XDC
Simulation
Model
Verilog
Supported
S/W Driver
Linux Driver
Tested Design Flows
(2)
Design Entry Vivado® Design Suite
Simulation
For supported simulators, see the
Xilinx Design Tools: Release Notes Guide.
Synthesis Vivado synthesis
Support
Provided by Xilinx at the Xilinx Support web page
Notes:
1. For a complete list of supported devices, see the Vivado IP
catalog.
2. For the supported versions of the tools, see the
Xilinx Design Tools: Release
Notes Guide.
