1.雅特力AT32F403A例程之-USB之HID双向通信

/** ************************************************************************** * @file at32f403a_407_emac.c * @version v2.0.7 * @date 2022-02-11 * @brief contains all the functions for the emac firmware library ************************************************************************** * Copyright notice & Disclaimer * * The software Board Support Package (BSP) that is made available to * download from Artery official website is the copyrighted work of Artery. * Artery authorizes customers to use, copy, and distribute the BSP * software and its related documentation for the purpose of design and * development in conjunction with Artery microcontrollers. Use of the * software is governed by this copyright notice and the following disclaimer. * * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES, * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS, * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS, * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT. * ************************************************************************** */ #include "at32f403a_407_conf.h" /** @addtogroup AT32F403A_407_periph_driver * @{ */ /** @defgroup EMAC * @brief EMAC driver modules * @{ */ #ifdef EMAC_MODULE_ENABLED /** @defgroup EMAC_private_functions * @{ */ #if defined (EMAC_BASE) /** * @brief global pointers on tx and rx descriptor used to track transmit and receive descriptors */ emac_dma_desc_type *dma_tx_desc_to_set; emac_dma_desc_type *dma_rx_desc_to_get; /* emac private function */ static void emac_delay(uint32_t delay); /** * @brief deinitialize the emac peripheral registers to their default reset values. * @param none * @retval none */ void emac_reset(void) { crm_periph_reset(CRM_EMAC_PERIPH_RESET, TRUE); crm_periph_reset(CRM_EMAC_PERIPH_RESET, FALSE); } /** * @brief initialize emac control structure * @param emac_control_config_type * @retval none */ void emac_control_para_init(emac_control_config_type *control_para) { control_para->auto_nego = EMAC_AUTO_NEGOTIATION_OFF; control_para->auto_pad_crc_strip = FALSE; control_para->back_off_limit = EMAC_BACKOFF_LIMIT_0; control_para->carrier_sense_disable = FALSE; control_para->deferral_check = FALSE; control_para->duplex_mode = EMAC_HALF_DUPLEX; control_para->fast_ethernet_speed = EMAC_SPEED_10MBPS; control_para->interframe_gap = EMAC_INTERFRAME_GAP_96BIT; control_para->ipv4_checksum_offload = FALSE; control_para->jabber_disable = FALSE; control_para->loopback_mode = FALSE; control_para->receive_own_disable = FALSE; control_para->retry_disable = FALSE; control_para->watchdog_disable = FALSE; } /** * @brief according to hclk to set mdc clock frequency. * @param none * @retval none */ void emac_clock_range_set(void) { uint8_t bits_value = 0; crm_clocks_freq_type clocks_freq = {0}; /* clear clock range bits */ EMAC->miiaddr_bit.cr = bits_value; crm_clocks_freq_get(&clocks_freq); if((clocks_freq.ahb_freq >= EMAC_HCLK_BORDER_20MHZ) && (clocks_freq.ahb_freq < EMAC_HCLK_BORDER_35MHZ)) { bits_value = EMAC_CLOCK_RANGE_20_TO_35; } else if((clocks_freq.ahb_freq >= EMAC_HCLK_BORDER_35MHZ) && (clocks_freq.ahb_freq < EMAC_HCLK_BORDER_60MHZ)) { bits_value = EMAC_CLOCK_RANGE_35_TO_60; } else if((clocks_freq.ahb_freq >= EMAC_HCLK_BORDER_60MHZ) && (clocks_freq.ahb_freq < EMAC_HCLK_BORDER_100MHZ)) { bits_value = EMAC_CLOCK_RANGE_60_TO_100; } else if((clocks_freq.ahb_freq >= EMAC_HCLK_BORDER_100MHZ) && (clocks_freq.ahb_freq < EMAC_HCLK_BORDER_150MHZ)) { bits_value = EMAC_CLOCK_RANGE_100_TO_150; } else if((clocks_freq.ahb_freq >= EMAC_HCLK_BORDER_150MHZ) && (clocks_freq.ahb_freq <= EMAC_HCLK_BORDER_240MHZ)) { bits_value = EMAC_CLOCK_RANGE_150_TO_240; } EMAC->miiaddr_bit.cr = bits_value; } /** * @brief configure emac control setting. * @param control_struct: control setting of mac control register. * @retval none */ void emac_control_config(emac_control_config_type *control_struct) { emac_deferral_check_set(control_struct->deferral_check); emac_backoff_limit_set(control_struct->back_off_limit); emac_auto_pad_crc_stripping_set(control_struct->auto_pad_crc_strip); emac_retry_disable(control_struct->retry_disable); emac_ipv4_checksum_offload_set(control_struct->ipv4_checksum_offload); emac_loopback_mode_enable(control_struct->loopback_mode); emac_receive_own_disable(control_struct->receive_own_disable); emac_carrier_sense_disable(control_struct->carrier_sense_disable); emac_interframe_gap_set(control_struct->interframe_gap); emac_jabber_disable(control_struct->jabber_disable); emac_watchdog_disable(control_struct->watchdog_disable); } /** * @brief reset emac dma * @param none * @retval none */ void emac_dma_software_reset_set(void) { EMAC_DMA->bm_bit.swr = 1; } /** * @brief get emac dma reset status * @param none * @retval TRUE of FALSE */ flag_status emac_dma_software_reset_get(void) { if(EMAC_DMA->bm_bit.swr) { return SET; } else { return RESET; } } /** * @brief enable emac and dma reception/transmission * @param none * @retval none */ void emac_start(void) { /* enable transmit state machine of the mac for transmission on the mii */ emac_trasmitter_enable(TRUE); /* flush transmit fifo */ emac_dma_operations_set(EMAC_DMA_OPS_FLUSH_TRANSMIT_FIFO, TRUE); /* enable receive state machine of the mac for reception from the mii */ emac_receiver_enable(TRUE); /* start dma transmission */ emac_dma_operations_set(EMAC_DMA_OPS_START_STOP_TRANSMIT, TRUE); /* start dma reception */ emac_dma_operations_set(EMAC_DMA_OPS_START_STOP_RECEIVE, TRUE); } /** * @brief stop emac and dma reception/transmission * @param none * @retval none */ void emac_stop(void) { /* stop dma transmission */ emac_dma_operations_set(EMAC_DMA_OPS_START_STOP_TRANSMIT, FALSE); /* stop dma reception */ emac_dma_operations_set(EMAC_DMA_OPS_START_STOP_RECEIVE, FALSE); /* stop receive state machine of the mac for reception from the mii */ emac_receiver_enable(FALSE); /* flush transmit fifo */ emac_dma_operations_set(EMAC_DMA_OPS_FLUSH_TRANSMIT_FIFO, TRUE); /* stop transmit state machine of the mac for transmission on the mii */ emac_trasmitter_enable(FALSE); } /** * @brief write phy data. * @param address: phy address. * @param reg: register of phy. * @param data: value that wants to write to phy. * @retval SUCCESS or ERROR */ error_status emac_phy_register_write(uint8_t address, uint8_t reg, uint16_t data) { uint32_t timeout = 0; EMAC->miidt_bit.md = data; EMAC->miiaddr_bit.pa = address; EMAC->miiaddr_bit.mii = reg; EMAC->miiaddr_bit.mw = 1; EMAC->miiaddr_bit.mb = 1; do { timeout++; } while((EMAC->miiaddr_bit.mb) && (timeout < PHY_TIMEOUT)); if(timeout == PHY_TIMEOUT) { return ERROR; } return SUCCESS; } /** * @brief read phy data * @param address: phy address. * @param reg: register of phy. * @param data: value that is read from phy. * @retval SUCCESS or ERROR */ error_status emac_phy_register_read(uint8_t address, uint8_t reg, uint16_t *data) { uint32_t timeout = 0; EMAC->miiaddr_bit.pa = address; EMAC->miiaddr_bit.mii = reg; EMAC->miiaddr_bit.mw = 0; EMAC->miiaddr_bit.mb = 1; do { *data = EMAC->miidt_bit.md; } while((EMAC->miiaddr_bit.mb) && (timeout < PHY_TI