Stratix II FPGA Power Guidelines
V
CCINT
(core voltage) 1.15 V min, 1.2 V typ, 1.25 V max
I
CCINT
(core current) To ensure correct selection of power
management circuitry it is recommended to use
Altera’s PowerPlay Power Estimation Tools to
obtain accurate results. Tools are available to
help determine power consumption before and
during the design process. More information on
these tools is available from Altera’s website:
www.altera.com/support/devices/estimator/
pow-powerplay.html
V
CCPD
(internal buffer voltage) 3.3 V typ
V
CCIO
(input/output voltages) 3.3 V, 2.5 V, 1.8 V and/or 1.5 V
I
CCIO
(input/output current) Up to 8 I/O banks @ up to 1.25 A each
Stratix and Stratix GX FPGA Power Guidelines
V
CCINT
(core) 1.5 V ± 5%
I
CCINT
(core) 250 mA to 10 A
I
CCINT
inrush to start-up EP1S10, EP1SGX10: 250 mA typ, 700 mA max
EP1S20: 400 mA typ, 1,200 mA max
EP1S25, EP1SGX25: 500 mA typ, 1,500 mA max
EP1S40, EP1SGX40: 650 mA typ, 2,300 mA max
EP1S60: 800 mA typ, 2,600 mA max
EP1S80: 1,000 mA typ, 3,000 mA max
V
CCIO
(I/O) 3.3 V, 2.5 V, 1.8 V and/or 1.5 V
I
CCIO
(I/O) Up to 8 I/O banks @ 50 mA to 1.5 A each
V
CC_PLL_OUT
3.3 V, 2.5 V, 1.8 V and/or 1.5 V
I
CC_PLL_OUT
50 mA (max)
Digital
(1)
voltages above Analog voltages below
V
CCA_PLL
1.5 V ± 5%
I
CC_PLL
200 mA (max) per PLL
Up to 12 each with separate V
CC
and GND
Additional Stratix GX Power Guidelines
Digital Transceiver Voltage: VCCP, VCCG 1.5 V ± 5%
ICC_Transceiver 250 mA (max) per transceiver
4 transceivers per block
Up to 5 blocks per device
Analog Transceiver Voltage: VCCR, VCCT 1.5 V ± 5%
ICC_Transceiver 250 mA (max) per transceiver
4 transceivers per block
Up to 5 blocks per device
Analog Transmitter Voltage: VCCAQ 3.3 V ± 5%
50 mA (max) per transceiver block
33
➔
➔
Texas Instruments 3Q 2005 Power Management FPGA/CPLD Reference Guide
Power Management FPGA and CPLD Reference Guide
Introduction
Texas Instruments (TI) works closely with Altera to recommend robust power solutions. On this page you will find a summary of the FPGA/CPLD
power guidelines. On page 2 is a comprehensive library of power designs. A listing of the TI DC/DC converter products that have been tested
and endorsed by Altera to power the listed devices is on page 4; schematics begin on page 6. Complete schematics and bill of materials (BOMs)
are available at www.ti.com/alterafpga. Please send questions to fpgasupport@list.ti.com.
This information is intended to provide the designer with a general understanding of the power guidelines of Altera FPGA/CPLD families in
typical applications. Please refer to the Altera Power Estimators, available at www.altera.com, for closer approximations specific to individual
FPGA/CPLD devices and applications.
Power Guidelines for Altera FPGAs and CPLDs
Cyclone FPGA Power Guidelines
V
CCINT
(core) 1.5 V ± 5%
I
CCINT
(core) 300 mA to 5 A
I
CCINT
inrush to start-up EC1C3: 300 mA max
EP1C4: 400 mA max
EP1C6: 500 mA max
EP1C12: 900 mA max
EP1C20: 1,200 mA max
V
CCIO
(I/O) 3.3 V, 2.5 V, 1.8 V and/or 1.5 V
I
CCIO
(I/O) Up to 4 I/O banks (50 mA to 1.5 A each)
Digital
(1)
voltages above Analog voltages below
V
CCA_PLL
(two) 1.5 V ± 5%
I
CC_PLL
200 mA (max) per PLL
MAX II CPLD Power Guidelines
V
CCINT
(core voltage) 2.375 V min, 2.5 V typ, 2.625 V max
(2.5 V or 3.3 V supported on all MAX II 3.00 V min, 3.3 V typ, 3.6 V max
without “G” ordering code. 1.8 V 1.71 V min, 1.8 V typ, 1.89 V max
supported with “G” ordering code.)
I
CCINT
(core current) EPM240: 30 mA typ, 75 mA max
EPM570: 40 mA typ, 125 mA max
EPM1270: 55 mA typ, 250 mA max
EPM2210: 75 mA typ, 400 mA max
I
CCINT
(inrush to start-up) 65 mA max
I
CCSTANDBY
12 mA typ
V
CCIO
(input/output voltages) 3.3 V, 2.5 V, 1.8 V and/or 1.5 V
I
CCIO
(input/output current) 25 to 50 mA each typ, 75 to 225 mA each max
(up to 4 I/O banks)
1
Digital voltages can be powered by linear or switching DC/DC converters. Linear regulators are recommended for analog voltages, for minimal noise.
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2010-09-21
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无聊闲逛2014-06-04不值得看，资料很差
