1GBDDR2 1GBDDR2

aaaaaaaaaaaaaaaaaDDR2 DDR2 dd = +1.8V ±0.1V, VddQ = +1.8V ±0.1V • JEDEC-standard 1.8V I/O (SSTL_18-compatible) • Differential data strobe (DQS, DQS#) option • 4n-bit prefetch architecture • Duplicate output strobe (RDQS) option for x8 • DLL to align DQ and DQS transitions with CK • 8 internal banks for concurrent operation • Programmable CAS latency (CL) • Posted CAS additive latency (AL) • WRITE latency = READ latency - 1 t CK • Selectable burst lengths (BL): 4 or 8 • Adjustable data-output drive st