Page 3 of 29
Rev. 1.4 Aug. 2005
DDR2 SDRAM
512Mb C-die DDR2 SDRAM
1.Key Features
Speed
DDR2-800
5-5-5
DDR2-667
5-5-5
DDR2-533
4-4-4
DDR2-400
3-3-3
Units
CAS Latency 5 5 43tCK
tRCD(min) 12.5 15 15 15 ns
tRP(min) 12.5 15 15 15 ns
tRC(min) 51.5 54 55 55 ns
0. Ordering Information
Note : Speed bin is in order of CL-tRCD-tRP.
Org. DDR2-800 5-5-5 DDR2-667 5-5-5 DDR2-533 4-4-4 DDR2-400 3-3-3 Package
128Mx4 K4T51043QC-ZC(L)E7 K4T51043QC-ZC(L)E6 K4T51043QC-ZC(L)D5 K4T51043QC-ZC(L)CC 60 FBGA
64Mx8 K4T51083QC-ZC(L)E7 K4T51083QC-ZC(L)E6 K4T51083QC-ZC(L)D5 K4T51083QC-ZC(L)CC 60 FBGA
32Mx16 K4T51163QC-ZC(L)E7 K4T51163QC-ZC(L)E6 K4T51163QC-ZC(L)D5 K4T51163QC-ZC(L)CC 84 FBGA
• JEDEC standard 1.8V ± 0.1V Power Supply
• VDDQ = 1.8V ± 0.1V
• 200 MHz f
CK
for 400Mb/sec/pin, 267MHz f
CK
for 533Mb/sec/
pin, 333MHz f
CK
for 667Mb/sec/pin, 400MHz f
CK
for 800Mb/
sec/pin
•4 Banks
• Posted CAS
• Programmable CAS Latency: 3, 4, 5
• Programmable Additive Latency: 0, 1 , 2 , 3 and 4
• Write Latency(WL) = Read Latency(RL) -1
• Burst Length: 4 , 8(Interleave/nibble sequential)
• Programmable Sequential / Interleave Burst Mode
• Bi-directional Differential Data-Strobe (Single-ended data-
strobe is an optional feature)
• Off-Chip Driver(OCD) Impedance Adjustment
• On Die Termination
• Special Function Support
-PASR(Partial Array Self Refresh)
-50ohm ODT
-High Temperature Self-Refresh rate enable
• Average Refresh Period 7.8us at lower than T
CASE
85°C,
3.9us at 85°C < T
CASE
< 95 °C
• All of Lead-free products are compliant for RoHS
The 512Mb DDR2 SDRAM is organized as a 32Mbit x 4 I/Os x 4
banks, 16Mbit x 8 I/Os x 4banks or 8Mbit x 16 I/Os x 4 banks
device. This synchronous device achieves high speed double-
data-rate transfer rates of up to 800Mb/sec/pin (DDR2-800) for
general applications.
The chip is designed to comply with the following key DDR2
SDRAM features such as posted CAS with additive latency, write
latency = read latency -1, Off-Chip Driver(OCD) impedance
adjustment and On Die Termination.
All of the control and address inputs are synchronized with a pair
of externally supplied differential clocks. Inputs are latched at the
crosspoint of differential clocks (CK rising and CK
falling). All I/Os
are synchronized with a pair of bidirectional strobes (DQS and
DQS
) in a source synchronous fashion. The address bus is used
to convey row, column, and bank address information in a RAS
/
CAS
multiplexing style. For example, 512Mb(x4) device receive
14/11/2 addressing.
The 512Mb DDR2 device operates with a single 1.8V ± 0.1V
power supply and 1.8V ± 0.1V VDDQ.
The 512Mb DDR2 device is available in 60ball FBGAs(x4/x8) and
in 84ball FBGAs(x16).
Note: The functionality described and the timing specifications
included in this data sheet are for the DLL Enabled mode of oper-
ation.
Note : This data sheet is an abstract of full DDR2 specification and does not cover the common features which are described in “Samsung’s DDR2
SDRAM Device Operation & Timing Diagram”
