RDA5780E芯片手册资源-CSDN文库

需积分: 19 7 浏览量 2010-05-05 09:43:29 上传评论收藏 689KB PDF 举报

《RDA5780E芯片手册：深度解析与应用》一、RDA5780E芯片概述 RDA5780E（在部分文档中提及为RDA5802E，可能存在型号命名差异）是RDA Microelectronics Inc.推出的一款高性能单芯片广播FM立体声调谐器，其设计旨在满足便携式设备对于高集成度、低功耗和卓越音频性能的需求。该芯片采用了先进的CMOS工艺，集成了合成器、中频(IF)选择性和MPX解码器等关键功能，从而实现了高度的集成化。二、核心特性详述 ### 1. CMOS单芯片全集成FM调谐器 RDA5780E采用CMOS工艺制造，具备高度集成性，将调谐器的所有必要组件集成于单一芯片之上，这不仅减少了外部组件的数量，还使得整个系统更为紧凑，适合用于空间有限的便携式设备。 ### 2. 低功耗在3.0V供电条件下，RDA5780E的总电流消耗低于22mA，展现出优异的能效比，这对于延长电池寿命、提高设备续航能力具有重要意义。 ### 3. 全球频率范围支持该芯片能够接收65-108MHz的全球广播FM频率，确保了在全球任何地区都能接收到广播信号，极大地扩展了其应用范围。 ### 4. 数字低中频（Low-IF）调谐器通过图像抑制下变频器、高性能模数转换器(A/D converter)以及内部执行的中频(IF)选择性，RDA5780E实现了高质量的音频处理，即便在接收条件变化时也能保持优良的音质。 ### 5. 高度集成的数字频率合成器内置的RF和IF压控振荡器(VCO)与闭环滤波器，使芯片无需外部元件即可完成频率合成，进一步减少了系统的复杂性和成本。 ### 6. 自主搜索调谐该功能允许芯片自动扫描频率，快速定位并锁定广播信号，提高了用户体验。 ### 7. 支持32.768KHz晶振这一特性保证了芯片的稳定运行，并提供了精确的时间基准。 ### 8. 数字自动增益控制(AGC) 通过数字AGC，RDA5780E可以自动调整接收信号的强度，确保即使在信号弱的情况下也能维持清晰的音质。 ### 9. 数字自适应噪声消除包括单声道/立体声切换、软静音和高切滤波等功能，有效降低了背景噪声，提升了音频的纯净度。 ### 10. 可编程去加重(50/75µs) 这一功能允许用户根据不同的广播标准调整音频信号的处理方式，增强了芯片的通用性。 ### 11. 接收信号强度指示器(RSSI) RSSI提供了信号强度的实时反馈，有助于评估接收质量，对调谐和调试过程至关重要。 ### 12. 低音增强通过内置的低音增强算法，RDA5780E能够在不牺牲音质的前提下提升低频响应，改善听觉体验。 ### 13. 音量控制用户可以通过芯片的接口调节音量大小，实现个性化的音频输出。 ### 14. I²S数字输出接口支持I²S数字音频接口，便于与数字音频处理器或播放器无缝连接。 ### 15. 线电平模拟输出电压提供线电平的模拟音频输出，适用于连接传统音响系统或耳机。 ### 16. 多种参考时钟选项支持32.768KHz、12M、24M、13M、26M、19.2M、38.4MHz等多种参考时钟输入，提高了系统设计的灵活性。 ### 17. 串行控制总线接口配备了2线和3线串行控制总线接口，简化了与微控制器的通信，便于系统集成。 ### 18. 直接支持32Ω负载无需额外的阻抗匹配电路，直接兼容32Ω的扬声器，减少了设计复杂度。 ### 19. 内置LDO稳压器集成的LDO稳压器支持1.8到5.5V的工作电压范围，为芯片提供了稳定的电源供给，增强了系统的鲁棒性。 ### 20. 小型封装采用4x4mm 24引脚QFN封装，尺寸紧凑，节省了PCB空间，适合小型化设计。三、应用场景 RDA5780E芯片广泛应用于各种便携式电子设备中，如： - 手机 - MP3/MP4播放器 - 便携式收音机 - PDA（个人数字助理） - 笔记本电脑其高集成度、低功耗和卓越的音频性能使其成为这些设备的理想选择，尤其是在空间受限和电池供电的应用场景中，RDA5780E的优势尤为明显。总结而言，RDA5780E芯片凭借其先进的设计、全面的功能和优异的性能，在便携式音频领域树立了新的标杆，为制造商提供了高效、灵活且经济的解决方案，推动了便携式设备向更高品质的音频体验迈进。

资源推荐

资源详情

资源评论

The information contained herein is the exclusive property of RDA and shall not be distributed, reproduced, or disclosed in whole or in

part without prior written permission of RDA.

RDA5802E

SINGLE-CHIP BROADCAST FM RADIO TUNER Rev.1.7–Jun.2009

1 General Description

The RDA5802E (RDA5802 Enhanced) is a

single-chip broadcast FM stereo radio tuner with

fully integrated synthesizer, IF selectivity and MPX

decoder. The tuner uses the CMOS process,

support multi-interface and require the least

external component. The package size is 4X4mm

and is completely adjustment-free. All these make

it very suitable for portable devices.

The RDA5802E has a powerful low-IF digital audio

processor, this make it have optimum sound quality

with varying reception conditions.

The RDA5802E can be tuned to the worldwide

frequency band.

1.1 Features

CMOS single-chip fully-integrated FM tuner

Low power consumption

Total current consumption lower than 22mA at 3.0V

power supply

Support worldwide frequency band

65 -108 MHz

Digital low-IF tuner

Image-reject down-converter

High performance A/D converter

IF selectivity performed internally

Fully integrated digital frequency synthesizer

Fully integrated on-chip RF and IF VCO

Fully integrated on-chip loop filter

Autonomous search tuning

Support 32.768KHz crystal oscillator

Digital auto gain control (AGC)

Digital adaptive noise cancellation

Mono/stereo switch

Soft mute

High cut

Programmable de-emphasis (50/75

Receive signal strength indicator (RSSI)

Bass boost

Volume control

S digital output interface

Line-level analog output voltage

32.768 KHz 12M,24M,13M,26M,19.2M,38.4MHz

Reference clock

2-wire and 3-wire serial control bus interface

Directly support 32Ω resistance loading

Integrated LDO regulator

1.8 to 5.5 V operation voltage

4X4mm 24 pin QFN package

1.2 Applications

Cellular handsets

MP3, MP4 players

Portable radios

，

PDAs, Notebook

Figure 1-1. RDA5802E Top View

RDA Microelectronics, Inc. RDA5802E FM Tuner V1.7

The information contained herein is the exclusive property of RDA and shall not be distributed, reproduced, or disclosed in whole or in

part without prior written permission of RDA. Page 2 of 23

2 Table of Contents

1 General Description....................................................................................................................................1

1.1 Features.........................................................................................................................................1

1.2

Applications

....................................................................................................................................1

2 Table of Contents........................................................................................................................................2

3 Functional Description...............................................................................................................................3

3.1 FM Receiver.................................................................................................................................3

3.2 Synthesizer....................................................................................................................................3

3.3 Power Supply................................................................................................................................3

3.4 RESET and Control Interface select.............................................................................................4

3.5 Control Interface...........................................................................................................................4

3.6 I

S Audio Data Interface...............................................................................................................4

3.7 GPIO Outputs...............................................................................................................................4

4 Electrical Characteristics...........................................................................................................................5

5 Receiver Characteristics.............................................................................................................................6

6 Serial Interface............................................................................................................................................7

6.1 Three-wire Interface Timing.........................................................................................................7

6.2 I

C Interface Timing.....................................................................................................................8

7 Register Definition......................................................................................................................................9

8 Pins Description........................................................................................................................................13

9 Application Diagram................................................................................................................................15

9.1 Audio Loading Resistance Larger than 32Ω & TCXO Application:..........................................15

9.1.1 Bill of Materials:.........................................................................................................................15

9.2 Audio Loading Resistance Lower than 32Ω & DCXO Application:..........................................16

9.2.1 Bill of Materials:.........................................................................................................................16

10 Package Physical Dimension....................................................................................................................17

11 PCB Land Pattern....................................................................................................................................18

12 Change List................................................................................................................................................21

13 Notes：.......................................................................................................................................................21

14 RDA5802E 与 RDA5802 对比..................................................................................................................22

15 Contact Information.................................................................................................................................23

RDA Microelectronics, Inc. RDA5802E FM Tuner V1.7

The information contained herein is the exclusive property of RDA and shall not be distributed, reproduced, or disclosed in whole or in

part without prior written permission of RDA. Page 3 of 23

3 Functional Description

Figure 3-1. RDA5802E FM Tuner Block Diagram

3.1 FM Receiver

The receiver uses a digital low-IF architecture that

avoids the difficulties associated with direct

conversion while delivering lower solution cost

and reduces complexity, and integrates a low

noise amplifier (LNA) supporting the FM

broadcast band (65 to 108MHz), a quadrature

image-reject mixer, a programmable gain control

(PGA), a high resolution analog-to-digital

converters (ADCs), an audio DSP and a high-

fidelity digital-to-analog converters (DACs).

The LNA has differential input ports (LNAP and

LNAN) and supports any input port by set

according registers bits (LNA_PORT_SEL[1:0]). It

default input common mode voltage is GND.

The limiter prevents overloading and limits the

amount of intermodulation products created by

strong adjacent channels.

The quadrature mixer down converts the LNA

output differential RF signal to low-IF, it also has

image-reject function.

The PGA amplifies the mixer output IF signal and

then digitized with ADCs.

The DSP core finishes the channel selection, FM

demodulation, stereo MPX decoder and output

audio signal. The MPX decoder can autonomous

switch from stereo to mono to limit the output

noise.

The DACs convert digital audio signal to analog

and change the volume at same time. The DACs

has low-pass feature and -3dB frequency is about

30 KHz.

3.2 Synthesizer

The frequency synthesizer generates the local

oscillator signal which divide to quadrature, then

be used to downconvert the RF input to a

constant low intermediate frequency (IF). The

synthesizer reference clock is 32.768 KHz.

The synthesizer frequency is defined by bits

CHAN[9:0] with the range from 65MHz to

108MHz.

3.3 Power Supply

The RDA5802E integrated one LDO which

supplies power to the chip. The external supply

RDA Microelectronics, Inc. RDA5802E FM Tuner V1.7

The information contained herein is the exclusive property of RDA and shall not be distributed, reproduced, or disclosed in whole or in

part without prior written permission of RDA. Page 4 of 23

voltage range is 1.8-5.5 V.

3.4 RESET and Control Interface select

The RDA5802E is RESET itself When VIO is

Power up. And also support soft reset by trigger

02H BIT1 from 0 to 1. The control interface is

select by MODE Pin. The MODE Pin is low ,I2C

Interface is select. The MODE Pin is set to VIO,

SPI Interface is select.

3.5 Control Interface

The RDA5802E supports three- wire and I

control interface. User could select either of them

to program the chip.

The three-wire interface is a standard SPI

interface. It includes three pins: SEN, SCLK and

SDIO. Each register write is 25-bit long, including

4-bit high register address, a r/w bit, 4-bit low

bit). RDA5802E samples command byte and data

at posedge of SCLK. Each register read is also

25-bit long, including 4-bit high register address, a

r/w bit, 4-bit low register address, and 16-bit data

(MSB is the first bit) from RDA5802E. The turn

around cycle between command byte from MCU

and data from RDA5802E is a half cycle.

RDA5802E samples command byte at posedge of

SCLK, and output data also at posedge of SCLK.

The I

C interface is compliant to I

C Bus

Specification 2.1. It includes two pins: SCLK and

SDIO. A I

C interface transfer begins with START

condition, a command byte and data bytes, each

byte has a followed ACK (or NACK) bit, and ends

with STOP condition. The command byte includes

a 7-bit chip address (0010000b) and a R/W bit.

The ACK (or NACK) is always sent out by receiver.

When in write transfer, data bytes is written out

from MCU, and when in read transfer, data bytes

is read out from RDA5802E. There is no visible

C interface transfers. The I

interface has a fixed start register address (0x02h

for write transfer and 0x0Ah for read transfer), and

an internal incremental address counter. If register

address meets the end of register file, 0x3Ah,

transfer, MCU programs registers from register

0x02h high byte, then register 0x02h low byte,

then register 0x03h high byte, till the last register.

RDA5802E always gives out ACK after every byte,

and MCU gives out STOP condition when register

programming is finished. For read transfer, after

command byte from MCU, RDA5802E sends out

byte, then register 0x0Bh high byte, till receives

NACK from MCU. MCU gives out ACK for data

bytes besides last data byte. MCU gives out

NACK for last data byte, and then RDA5802E will

return the bus to MCU, and MCU will give out

STOP condition.

Details refer to RDA5802E Programming Guide.

3.6 I

S Audio Data Interface

The RDA5802E supports I

S (Inter_IC Sound Bus)

audio interface. The interface is fully compliant

with I

S bus specification. When setting I2SEN bit

high, RDA5802E will output SCK, WS, SD signals

from GPIO3, GPIO1, GPIO2 as I

S master and

transmitter, the sample rate is 48Kbps ，

44.1kbps,32kbps….. RDA5802E also support as

S slaver mode and transmitter, the sample rate

is less than 100kbps.

Details refer to RDA5802E Programming Guide.

3.7 GPIO Outputs

The RDA5802E has three GPIOs. The function of

GPIOs could programmed with bits GPIO1[1:0],

GPIO2[1:0], GPIO3[1:0] and I2SEN.

If I2SEN is set to low, GPIO pins could be

programmed to output low or high or high-Z, or be

programmed to output interrupt and stereo

indicator with bits GPIO1[1:0], GPIO2[1:0],

GPIO3[1:0]. GPIO2 could be programmed to

output a low interrupt (interrupt will be generated

only with interrupt enable bit STCIEN is set to high)

when seek/tune process completes. GPIO3 could

be programmed to output stereo indicator bit ST.

Constant low, high or high-Z functionality is

available regardless of the state of VA and VD

supplies or the ENABLE bit.

剩余22页未读，继续阅读

评论收藏

内容反馈

slq19870609

粉丝: 3
资源: 1

RDA5780E芯片手册

RDA5851S开发手册

RDA5280技术手册

RDA8851芯片开发手册

RDA1845编程手册

RDA1845编程手册V2.3

RDA8851软件开发手册.rar

RDA5851S_Chip_Datasheet 数据手册

RDA5981_SDK开发手册-V1.1.01

RDA5820中文参考手册，中文翻译

RDA5888E高频头专用芯片

RDA7088 调频收音机芯片.pdf

RDA5807收音机芯片详细说明

RDA5981_SDK开发手册-V1.1.3.rar_RDA5981 pdf_historyeeh_rda5981_rda598

RDA5851完整规格书

RDA5807资料

RDA5807编程指南

RDA5807应用说明

芯片手册资料

RDA6625E_datasheet_V0.1.pdf

紫光展锐8503芯片手册

基于RDA5856TE芯片蓝牙音箱硬件参考设计PADS9.5原理图+蛇形和倒F形天线封装pads9.5 PCB图.zip

基于RDA5820的芯片功能扩展(DOC).pdf

RDA5820_datasheet.pdf

一些芯片的数据手册

芯片数据手册

RDA5820.rar_430 rda5820_RDA5820_RDA5820 PDF_rda5820 datashe_rda

实现RDA的详细配置说明

最新资源