clk I
rst I
.
1.
datapath_PPL
. .
. .
⇥. ⇥.
`include"PC_PPL.v"
`include"IUnit.v"
`include"IF_ID.v"
`include"ID.v"
`include"ID_EX.v"
`include"EX.v"
`include"EX_Mem.v"
`include"Mem.v"
`include"Mem_Wr.v"
`include"Wr.v"
`include"Pre_Data_Hazard.v"
`include"branch_Data_Hazard.v"
`include"MULT_Data_Hazard.v"
`include"CPR_Data_Hazard.v"
`include"ERET_Data_Hazard.v"
`include"Load_use.v"
module datapath_PPL(clk,rst);
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input clk,rst;
wire[31:2] PC,NPC;
wire[31:2] IF_PC,ID_PC,EX_PC,Mem_PC,Wr_PC;
wire[31:0] instruction,ID_instruction,pre_instruction;
wire sign,signal;
wire[31:0] E,F;
wire ID_Jump,EX_Jump;
wire ID_Branch,EX_Branch;
wire[5:0] ID_op,EX_op,Mem_op,Wr_op;
wire[4:0] ID_rs,EX_rs,Mem_rs,Wr_rs;
wire[4:0] ID_rt,EX_rt,Mem_rt,Wr_rt;
wire[4:0] ID_rd,EX_rd,Mem_rd,Wr_rd;
wire[4:0] ID_shamt,EX_shamt,Mem_shamt,Wr_shamt;
wire[5:0] ID_func,EX_func,Mem_func,Wr_func;
wire[15:0] ID_imm16,EX_imm16;
wire[25:0] ID_target,EX_target;
wire[31:0] ID_busA,EX_busA,Mem_busA,Wr_busA;
wire[31:0] ID_busB,EX_busB,Mem_busB,Wr_busB;
wire ID_RegDst,EX_RegDst,Mem_RegDst,Wr_RegDst;
wire ID_RegWr,EX_RegWr,Mem_RegWr,Wr_RegWr;
wire ID_ALUSrc,EX_ALUSrc;
wire ID_MemWr,EX_MemWr,Mem_MemWr;
wire ID_MemtoReg,EX_MemtoReg,Mem_MemtoReg,Wr_MemtoReg;
wire[1:0] ID_ExtOp,EX_ExtOp;
wire[4:0] ID_ALUctr,EX_ALUctr;
wire[31:0] alure,Mem_alure,Wr_alure;
wire[4:0] EX_Reg,Mem_Reg,Wr_Reg;
wire[31:0] Mem_dout,Wr_dout;
wire[31:0] Wr_busW;
!"wire[1:0] ALUSrcA,ALUSrcB;
wire[31:0] A,B;
wire[1:0] ALUSrcC,ALUSrcD;
wire[1:0] ALUSrcE,ALUSrcF;
wire Load_use;
wire EX_MemRead;
!"wire[31:0] ID_hi_num;
wire[31:0] EX_hi_num;
!"wire[31:0] ID_lo_num;
wire[31:0] EX_lo_num;
wire[63:0] EX_MULT_result,Mem_MULT_result,Wr_MULT_result;
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