################################################################################
# Vivado (TM) v2019.1 (64-bit)
#
# README.txt: Please read the sections below to understand the steps required
# to simulate the design for a simulator, the directory structure
# and the generated exported files.
#
################################################################################
1. Simulate Design
To simulate design, cd to the simulator directory and execute the script.
For example:-
% cd questa
% ./top.sh
The export simulation flow requires the Xilinx pre-compiled simulation library
components for the target simulator. These components are referred using the
'-lib_map_path' switch. If this switch is specified, then the export simulation
will automatically set this library path in the generated script and update,
copy the simulator setup file(s) in the exported directory.
If '-lib_map_path' is not specified, then the pre-compiled simulation library
information will not be included in the exported scripts and that may cause
simulation errors when running this script. Alternatively, you can provide the
library information using this switch while executing the generated script.
For example:-
% ./top.sh -lib_map_path /design/questa/clibs
Please refer to the generated script header 'Prerequisite' section for more details.
2. Directory Structure
By default, if the -directory switch is not specified, export_simulation will
create the following directory structure:-
<current_working_directory>/export_sim/<simulator>
For example, if the current working directory is /tmp/test, export_simulation
will create the following directory path:-
/tmp/test/export_sim/questa
If -directory switch is specified, export_simulation will create a simulator
sub-directory under the specified directory path.
For example, 'export_simulation -directory /tmp/test/my_test_area/func_sim'
command will create the following directory:-
/tmp/test/my_test_area/func_sim/questa
By default, if -simulator is not specified, export_simulation will create a
simulator sub-directory for each simulator and export the files for each simulator
in this sub-directory respectively.
IMPORTANT: Please note that the simulation library path must be specified manually
in the generated script for the respective simulator. Please refer to the generated
script header 'Prerequisite' section for more details.
3. Exported script and files
Export simulation will create the driver shell script, setup files and copy the
design sources in the output directory path.
By default, when the -script_name switch is not specified, export_simulation will
create the following script name:-
<simulation_top>.sh (Unix)
When exporting the files for an IP using the -of_objects switch, export_simulation
will create the following script name:-
<ip-name>.sh (Unix)
Export simulation will create the setup files for the target simulator specified
with the -simulator switch.
For example, if the target simulator is "ies", export_simulation will create the
'cds.lib', 'hdl.var' and design library diectories and mappings in the 'cds.lib'
file.
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MT9M034.rar
共244个文件
v:24个
txt:22个
pb:19个
需积分: 50 11 下载量 42 浏览量
2020-01-19
11:45:59
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实现MT9M034图像传感器数据的基本接收,内部包括完整的接口工程,上电后的寄存及基本配置,目前当前配置是行长640,行数480,所以每帧数据共640*480=307200个数据,理论与实际板子上接到的数据情况是一致的,可见功能正确。
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MT9M034.rar (244个子文件)
__synthesis_is_complete__ 0B
__synthesis_is_complete__ 0B
runme.bat 229B
runme.bat 229B
runme.bat 229B
MT9M034_RX.bit 10.91MB
MT9M034_RX_routed.dcp 3.05MB
MT9M034_RX_placed.dcp 2.71MB
MT9M034_RX_opt.dcp 1.98MB
u_ila_0.dcp 661KB
u_ila_1.dcp 532KB
dbg_hub.dcp 358KB
MT9M034_RX.dcp 194KB
MT9M034_RX.dcp 57KB
clk_gen.dcp 9KB
clk_gen.dcp 9KB
clk_gen.dcp 9KB
compile.do 667B
compile.do 643B
compile.do 602B
compile.do 592B
simulate.do 307B
simulate.do 300B
simulate.do 300B
simulate.do 191B
elaborate.do 179B
wave.do 32B
wave.do 32B
wave.do 32B
wave.do 32B
simulate.do 11B
run.f 454B
run.f 438B
usage_statistics_webtalk.html 37KB
hw_ila_data_1.ila 32KB
xsim.ini 25KB
vivado.jou 684B
vivado.jou 676B
vivado.jou 671B
ISEWrap.js 8KB
ISEWrap.js 8KB
ISEWrap.js 8KB
rundef.js 1KB
rundef.js 1KB
rundef.js 1KB
runme.log 35KB
runme.log 34KB
runme.log 23KB
MT9M034.lpr 343B
MT9M034_RX.ltx 12KB
debug_nets.ltx 12KB
elab.opt 184B
messagePromote.pb 472KB
vivado.pb 55KB
vivado.pb 37KB
place_design.pb 18KB
route_design.pb 15KB
opt_design.pb 15KB
write_bitstream.pb 8KB
init_design.pb 3KB
MT9M034_RX_power_summary_routed.pb 740B
MT9M034_RX_utilization_placed.pb 289B
clk_gen_utilization_synth.pb 289B
MT9M034_RX_utilization_synth.pb 289B
vivado.pb 149B
MT9M034_RX_timing_summary_routed.pb 109B
MT9M034_RX_drc_routed.pb 75B
MT9M034_RX_methodology_drc_routed.pb 53B
MT9M034_RX_route_status.pb 44B
MT9M034_RX_drc_opted.pb 37B
MT9M034_RX_bus_skew_routed.pb 36B
MT9M024-M034_REG.pdf 1.37MB
MT9M034-D.PDF 357KB
vlog.prj 231B
MT9M034_RX_timing_summary_routed.rpt 674KB
MT9M034_RX_io_placed.rpt 207KB
MT9M034_RX_methodology_drc_routed.rpt 120KB
MT9M034_RX_control_sets_placed.rpt 99KB
MT9M034_RX_bus_skew_routed.rpt 67KB
MT9M034_RX_clock_utilization_routed.rpt 35KB
MT9M034_RX_utilization_placed.rpt 10KB
MT9M034_RX_power_routed.rpt 10KB
MT9M034_RX_utilization_synth.rpt 7KB
clk_gen_utilization_synth.rpt 7KB
MT9M034_RX_drc_routed.rpt 5KB
MT9M034_RX_drc_opted.rpt 3KB
MT9M034_RX_route_status.rpt 651B
MT9M034_RX_power_routed.rpx 2.58MB
MT9M034_RX_timing_summary_routed.rpx 719KB
MT9M034_RX_methodology_drc_routed.rpx 213KB
MT9M034_RX_bus_skew_routed.rpx 106KB
MT9M034_RX_drc_routed.rpx 7KB
MT9M034_RX_drc_opted.rpx 2KB
.vivado.begin.rst 217B
.vivado.begin.rst 217B
.vivado.begin.rst 216B
.init_design.begin.rst 177B
.place_design.begin.rst 177B
.write_bitstream.begin.rst 177B
.opt_design.begin.rst 177B
共 244 条
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