Overview
Wide parallel memory busses can present significant design challenges when it comes
to designing a robust power delivery network (PDN). One critical focus of PDN design is
delivery of power to the memory chip output drivers. The on-chip data (DQ) drivers can
require significant amounts of current delivered through sometimes highly inductive
package connections. Low power dual data rate (LPDDR) devices can have up to 32 DQ
drivers on one die switching at the same time. Stacked die packages can increase this
number for a single package. These simultaneous switching outputs can cause signifi-
cant noise issues that translate into timing jitter and SI problems.
Mitigating system SSO issues requires optimizing the PDN design of the printed circuit
board (PCB), the package, and on the die. Detailed circuit models are needed for each
piece. Historically, these circuit models are combined and simulated in SPICE-based
simulators to analyze SSO effects. These simulations are computationally intensive and
lead to lengthy simulation times from hours to days.
SPICE-based transistor level models of the on-die drivers are often the most complex
part of the system model. This is especially true for the most accurate models that in-
clude layout-based RC parasitic circuit elements, typical of Micron's DRAM buffer mod-
els. One effective way to reduce simulation time is to use behavioral buffer models. Be-
havioral models use simpler algorithms than SPICE models, enabling faster simulation
with often similar levels of accuracy.
IBIS 5.0 Power Integrity Features
At its core, an IBIS model uses only a few tables of data to represent the behavioral char-
acteristics of a buffer. Sets of I-V tables represent the I
DS
versus V
DS
characteristics of
the pull-down and pull-up transistors, showing the dynamic impedance of the buffer.
The switching behavior of the buffer is shown through sets of V-T tables that capture the
rising and falling edge transitions of the buffer driving resistive test loads. The capaci-
tance of the buffer is also quantified. This information provides an accurate model for
SI simulation, but it lacks behavioral characteristics necessary for PI simulation.
One of the major upgrades in the IBIS version 5.0 specification is the introduction of ad-
ditional data tables to model buffer power characteristics. Models containing these data
are known as power-aware IBIS models. Model data within an IBIS file is contained in
sections headed by keywords in brackets. The new keywords in IBIS 5.0 specific to PI
include [Composite Current], [ISSO PU], and [ISSO PD].
[Composite Current] Data
[Composite Current] data are I-T tables that describe the shape of the rising and falling
edge current waveforms from the power reference terminal of the buffer.
The I-T tables show the switching current associated with the V-T tables. As shown in
Figure 1 (page 3), this switching current includes contributions from the on-die de-
coupling circuit (I_byp), crow-bar current (I_cb), any termination current (I_term), sig-
nal driver current (I_sig), and pre-driver current (I_pre). The pre-driver current is the
most significant current contribution besides the final driver current seen in DRAM de-
vice drivers. Final driver current could be derived accurately by simulating pre-IBIS 5.0
models; however, this significantly underestimates the total driver current without de-
tails of the pre-driver contribution.
TN-00-33: Power Integrity Simulation with IBIS 5.0 Models
Overview
PDF: 09005aef866937be
tn0033_ibis_models_power_integrity_simulation.pdf - Rev. A 1/16
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