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###############################################################################
## ____ ____
## / /\/ /
## /___/ \ / Vendor : Xilinx
## \ \ \/ Version : 4.2
## \ \ Application : MIG
## / / Filename : readme.txt
## /___/ /\ Date Last Modified : $Date: 2011/06/02 08:31:16 $
## \ \ / \ Date Created : Tue Sept 21 2010
## \___\/\___\
##
## Device : 7 Series
## Design Name : DDR3 SDRAM
## Purpose : Steps to run simulations using Modelsim/QuestaSim,
## Cadence IES, and Synopsys VCS
## Assumptions : Simulations are run in \sim folder of MIG output "Open IP
## Example Design" directory
## Reference :
## Revision History:
###############################################################################
MIG outputs script files required to run the simulations for Modelsim/QuestaSim,
Vivado Simulator, IES and VCS. These scripts are valid only for running
simulations for "Open IP Example Design"
1. How to run simulations in Modelsim/QuestaSim simulator
A) sim.do File :
a) The 'sim.do' file has commands to compile and simulate memory
interface design and run the simulation for specified period of time.
b) It has the syntax to Map the required libraries (unisims_ver,
unisim and secureip). The libraries should be mapped using
the following command
vmap unisims_ver <unisims_ver lib path>
vmap unisim <unisim lib path>
vmap secureip <secureip lib path>
Also, $XILINX_VIVADO environment variable must be set in order to compile glbl.v file
c) Displays the waveforms that are listed with "add wave" command.
B) Steps to run the Modelsim/QuestaSim simulation:
a) The user should invoke the Modelsim/QuestaSim simulator GUI.
b) Change the present working directory path to the sim folder.
In Transcript window, at Modelsim/QuestaSim prompt, type the following
command to change directory path.
cd <sim directory path>
c) Run the simulation using sim.do file.
At Modelsim/QuestaSim prompt, type the following command:
do sim.do
d) To exit simulation, type the following command at Modelsim/QuestaSim
prompt:
quit -f
e) Verify the transcript file for the memory transactions.
2. How to run simulations in Vivado simulator
A) Following files are provided :
a) The 'xsim_run.bat' is the executable file for Vivado simulator under
MicroSoft Windows environment.
b) The 'xsim_run.sh' is the executable file for Vivado simulator under
Linux environment.
c) The 'xsim_run.bat'/'xsim_run.sh' file has commands to compile and
simulate memory interface design and run the simulation for specified
period of time.
d) xsim_options.tcl file has commands to add waveforms and simulation
period.
e) xsim_files.prj file has list of rtl files for simulating the design.
f) $XILINX_VIVADO environment variable must be set in order to compile
glbl.v file
B) Steps to run the Vivado Simulator simulation:
a) Change the present working directory path to the sim folder of "Open
IP Example Design" path in the OS terminal.
b) Run the simulation using xsim_run.sh file under Linux environment and
xsim_run.bat under MicroSoft Windows environment.
c) Verify the transcript file for the memory transactions.
3. How to run Cadence IES Simulations
A) ies_run.sh File :
a) The "ies_run.sh" file contains the commands for simulation of the
hdl files.
b) Libraries must be mapped before running simulations. Following
procedure must be followed to before running simulations
1. Create two files named cds.lib and hdl.var in this directory
2. Create a directory 'worklib' in same directory.
mkdir worklib
3. Add following lines in the cds.lib file to map Xilinx libraries
DEFINE unisim /proj/xbuilds/2014.4_daily_latest/clibs/ius/13.20.005/lin64/lib/./unisim
DEFINE unisims_ver /proj/xbuilds/2014.4_daily_latest/clibs/ius/13.20.005/lin64/lib/./unisims_ver
DEFINE secureip /proj/xbuilds/2014.4_daily_latest/clibs/ius/13.20.005/lin64/lib/./secureip
DEFINE worklib ./worklib
4. ATTENTION: In above lines replace the path for libraries as per your
compiled Xilinx libraries directory
5. ATTENTION: Add the lines in the same order given above
6. Please make sure you need to map all Xilinx libraries mentioned above
7. Save and close the cds.lib file
Also, $XILINX_VIVADO environment variable must be set in order to
compile glbl.v file and the above mentioned library files
B) Steps to run the IES simulation:
a) Change the present working directory path to the sim folder of "Open
IP Example Design" path in the OS terminal.
b) Run the simulation using ies_run.sh file. Type the following command:
./ies_run.sh
c) Verify the ies_sim.log file for the memory transactions.
4. How to run Synopsys VCS Simulations
A) vcs_run.sh Fi
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fpga pcie dma参考例程xapp1171 仿真工程 (1060个子文件)
__synthesis_is_complete__ 0B
__synthesis_is_complete__ 0B
__synthesis_is_complete__ 0B
__synthesis_is_complete__ 0B
__synthesis_is_complete__ 0B
__synthesis_is_complete__ 0B
__synthesis_is_complete__ 0B
__synthesis_is_complete__ 0B
__synthesis_is_complete__ 0B
__synthesis_is_complete__ 0B
xsim_run.bat 3KB
xsim_run.bat 3KB
runme.bat 229B
runme.bat 229B
runme.bat 229B
runme.bat 229B
runme.bat 229B
runme.bat 229B
runme.bat 229B
runme.bat 229B
runme.bat 229B
runme.bat 229B
pcie_dma.bd 62KB
pcie_dma.bxml 11KB
pcie_dma_axi_pcie_0_0.dcp 5.81MB
pcie_dma_axi_pcie_0_0.dcp 5.81MB
pcie_dma_axi_pcie_0_0.dcp 5.8MB
pcie_dma_axi_pcie_0_0.dcp 4.83MB
pcie_dma_mig_7series_0_0.dcp 4.14MB
pcie_dma_mig_7series_0_0.dcp 4.14MB
pcie_dma_mig_7series_0_0.dcp 4.13MB
pcie_dma_xbar_1.dcp 2.22MB
pcie_dma_xbar_1.dcp 2.22MB
pcie_dma_xbar_1.dcp 2.22MB
pcie_dma_axi_cdma_0_0.dcp 878KB
pcie_dma_axi_cdma_0_0.dcp 878KB
pcie_dma_axi_cdma_0_0.dcp 876KB
pcie_dma_auto_us_df_2.dcp 853KB
pcie_dma_auto_us_df_2.dcp 853KB
pcie_dma_auto_us_df_2.dcp 851KB
pcie_dma_auto_us_df_0.dcp 815KB
pcie_dma_auto_us_df_0.dcp 815KB
pcie_dma_auto_us_df_1.dcp 780KB
pcie_dma_auto_us_df_1.dcp 780KB
pcie_dma_auto_cc_1.dcp 708KB
pcie_dma_auto_cc_1.dcp 708KB
pcie_dma_auto_cc_0.dcp 704KB
pcie_dma_auto_cc_0.dcp 704KB
pcie_dma_auto_ds_3.dcp 618KB
pcie_dma_auto_ds_3.dcp 618KB
pcie_dma_auto_ds_3.dcp 618KB
pcie_dma_auto_ds_1.dcp 589KB
pcie_dma_auto_ds_1.dcp 589KB
pcie_dma_auto_ds_2.dcp 589KB
pcie_dma_auto_ds_3.dcp 588KB
pcie_dma_auto_ds_0.dcp 558KB
pcie_dma_auto_ds_0.dcp 558KB
pcie_dma_auto_pc_0.dcp 239KB
pcie_dma_auto_pc_0.dcp 239KB
pcie_dma_auto_pc_1.dcp 239KB
pcie_dma_axi_bram_ctrl_0_0.dcp 216KB
pcie_dma_axi_bram_ctrl_0_0.dcp 216KB
pcie_dma_axi_bram_ctrl_0_0.dcp 215KB
pcie_dma_blk_mem_gen_0_0.dcp 120KB
pcie_dma_blk_mem_gen_0_0.dcp 120KB
pcie_dma_blk_mem_gen_0_0.dcp 120KB
pcie_dma_s02_mmu_0.dcp 111KB
pcie_dma_s01_mmu_0.dcp 97KB
pcie_dma_rst_mig_7series_0_200M_1.dcp 21KB
pcie_dma_rst_mig_7series_0_200M_1.dcp 21KB
pcie_dma_rst_mig_7series_0_200M_1.dcp 21KB
pcie_dma_rst_axi_pcie_0_125M_1.dcp 21KB
pcie_dma_rst_axi_pcie_0_125M_1.dcp 21KB
pcie_dma_rst_axi_pcie_0_125M_1.dcp 21KB
compile.do 24KB
compile.do 23KB
compile.do 23KB
compile.do 16KB
sim.do 7KB
sim.do 7KB
simulate.do 843B
simulate.do 837B
simulate.do 837B
elaborate.do 715B
simulate.do 193B
wave.do 32B
wave.do 32B
wave.do 32B
wave.do 32B
simulate.do 11B
run.f 20KB
run.f 20KB
pcie_dma.hwdef 67KB
pcie_dma.hwh 584KB
xil_txt.in 1KB
modelsim.ini 137KB
xsim.ini 22KB
vivado.jou 916B
vivado.jou 895B
vivado.jou 867B
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