Power.org™ Standard for Embedded Power
Architecture™ Platform Requirements (ePAPR)
Version 1.0 – 23 July 2008
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Version 1.0 – 23 July 2008 Power.org ePAPR
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LICENSE INFORMATION
©
Copyright 2008 Power.org, Inc
© Copyright Freescale Semiconductor, Inc., 2008
© Copyright International Business Machines Corporation, 2008
All Rights Reserved.
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Table of Contents
Revision History ................................................................................................................. 8
1 Introduction................................................................................................................. 9
1.1 Purpose and Scope.............................................................................................. 9
1.2 Relationship to IEEE™ 1275............................................................................ 11
1.3 32-bit and 64-bit Support.................................................................................. 11
1.4 References......................................................................................................... 12
1.5 Definition of Terms........................................................................................... 14
1.6 Organizationally Unique Identifiers ................................................................. 15
2 The Device Tree........................................................................................................ 16
2.1 Overview........................................................................................................... 16
2.2 Device Tree Structure and Conventions ........................................................... 17
2.2.1 Node Names.............................................................................................. 17
2.2.1.1 Node Name Requirements.................................................................... 17
2.2.2 Generic Names Recommendation............................................................. 19
2.2.3 Path Names ............................................................................................... 20
2.2.4 Properties .................................................................................................. 20
2.2.4.1 Property Names..................................................................................... 20
2.2.4.2 Property Values..................................................................................... 21
2.3 Standard Properties........................................................................................... 23
2.3.1 compatible................................................................................................. 23
2.3.2 model......................................................................................................... 23
2.3.3 phandle...................................................................................................... 24
2.3.4 status ......................................................................................................... 25
2.3.5 #address-cells and #size-cells ................................................................... 26
2.3.6 reg ............................................................................................................. 27
2.3.7 virtual-reg.................................................................................................. 27
2.3.8 ranges........................................................................................................ 28
2.3.9 dma-ranges................................................................................................ 30
2.3.10 name.......................................................................................................... 31
2.3.11 device_type ............................................................................................... 31
2.4 Interrupts and Interrupt Mapping...................................................................... 32
2.4.1 Properties for Interrupt Generating Devices............................................. 34
2.4.1.1 interrupts ............................................................................................... 34
2.4.1.2 interrupt-parent ..................................................................................... 34
2.4.2 Properties for Interrupt Controllers........................................................... 35
2.4.2.1 #interrupt-cells...................................................................................... 35
2.4.2.2 interrupt-controller................................................................................ 35
2.4.3 Interrupt Nexus Properties........................................................................ 35
2.4.3.1 interrupt-map......................................................................................... 35
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2.4.3.2 interrupt-map-mask............................................................................... 36
2.4.3.3 #interrupts-cells..................................................................................... 36
2.4.4 Interrupt Mapping Example...................................................................... 37
3 Device Node Requirements ...................................................................................... 39
3.1 Base Device Node Types.................................................................................. 39
3.2 Root node.......................................................................................................... 39
3.3 aliases node....................................................................................................... 40
3.4 Memory node.................................................................................................... 41
3.5 Chosen............................................................................................................... 42
3.6 CPUS Node Properties...................................................................................... 43
3.7 CPU Node Properties........................................................................................ 43
3.7.1 General Properties of CPU nodes ............................................................. 43
3.7.2 TLB Properties.......................................................................................... 45
3.7.3 Internal (L1) Cache Properties.................................................................. 45
3.7.4 Example .................................................................................................... 46
3.8 Multi-level and Shared Caches......................................................................... 47
4 Client Program Image Format .................................................................................. 49
4.1 Variable Address Image Format....................................................................... 49
4.1.1 ELF Basics................................................................................................ 49
4.1.2 Boot Program Requirements..................................................................... 50
4.1.2.1 Processing of PT_LOAD segments ...................................................... 50
4.1.2.2 Entry point ............................................................................................ 50
4.1.3 Client Program Requirements................................................................... 51
4.2 Fixed Address Image Format............................................................................ 51
5 Client Program Boot Requirements.......................................................................... 52
5.1 Boot and Secondary CPUs................................................................................ 52
5.2 Device Tree....................................................................................................... 52
5.3 Initial Mapped Areas......................................................................................... 53
5.4 CPU Entry Point Requirements ........................................................................ 54
5.4.1 Boot CPU Initial Register Values............................................................. 54
5.4.2 I/O Devices State ...................................................................................... 55
5.4.3 Initial I/O Mappings (IIO) ........................................................................ 55
5.4.4 Boot CPU Entry Requirements: Real Mode............................................. 55
5.4.5 Boot CPU Entry Requirements for IMAs: Book IIII-E............................ 56
5.4.6 Secondary CPU Entry Requirements; Real Mode.................................... 57
5.4.7 Secondary CPU Entry Requirements for IMAs -- Book III-E.................. 57
5.5 Symmetric Multiprocessing (SMP) Boot Requirements .................................. 58
5.5.1 Overview................................................................................................... 58
5.5.2 Spin Table................................................................................................. 59
5.5.2.1 Overview............................................................................................... 59
5.5.2.2 Boot Program Requirements................................................................. 60
5.5.2.3 Client Program Requirements............................................................... 61
5.5.3 Implementation-Specific Release from Reset........................................... 61
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5.5.4 Timebase Synchronization........................................................................ 61
5.6 Asymmetric Configuration Considerations ...................................................... 61
6 Device Bindings........................................................................................................ 62
6.1 Binding Guidelines ........................................................................................... 62
6.1.1 General Principles..................................................................................... 62
6.1.2 Miscellaneous Properties .......................................................................... 63
6.1.2.1 clock-frequency..................................................................................... 63
6.1.2.2 reg-shift................................................................................................. 63
6.2 PCI and PCI Express......................................................................................... 64
6.2.1 Overview................................................................................................... 64
6.2.2 PCI Address Representation ..................................................................... 64
6.2.3 Configuration Space.................................................................................. 65
6.2.4 I/O Space................................................................................................... 66
6.2.5 Memory Space.......................................................................................... 67
6.2.6 Hard-decoded Spaces................................................................................ 68
6.2.7 Bus nodes.................................................................................................. 69
6.2.8 Child nodes ............................................................................................... 70
6.3 ISA and Legacy Devices................................................................................... 71
6.3.1 ISA Interrupt Controllers.......................................................................... 71
6.4 Serial devices .................................................................................................... 72
6.4.1 Serial Class Binding.................................................................................. 72
6.4.1.1 clock-frequency..................................................................................... 72
6.4.1.2 current-speed......................................................................................... 72
6.4.2 National Semiconductor 16450/16550 Compatible UART Requirements73
6.5 Network devices................................................................................................ 73
6.5.1 Network Class Binding............................................................................. 73
6.5.1.1 address-bits ........................................................................................... 73
6.5.1.2 local-mac-address ................................................................................. 74
6.5.1.3 mac-address........................................................................................... 74
6.5.1.4 max-frame-size ..................................................................................... 74
6.5.2 Ethernet specific considerations ............................................................... 74
6.5.2.1 max-speed ............................................................................................. 75
6.5.2.2 phy-connection-type ............................................................................. 75
6.5.2.3 phy-handle............................................................................................. 75
6.6 Device Control Register (DCR) Devices.......................................................... 76
6.6.1 DCR Controller Requirements.................................................................. 76
6.6.1.1 dcr-reg................................................................................................... 76
6.6.1.2 dcr-parent.............................................................................................. 76
6.6.2 DCR Programmed Device Requirements................................................. 77
6.6.2.1 dcr-controller......................................................................................... 77
6.6.2.2 dcr-access-method................................................................................. 77
6.7 open PIC Interrupt Controllers.......................................................................... 78
6.8 simple-bus......................................................................................................... 78
