Copyright © 2008, 2011 Power.org, Inc. All Rights Reserved.
Power.org™ Standard for Embedded Power Architecture™ Platform Requirements
(ePAPR)
Version 1.1 – 08 April 2011
Copyright © 2008,2011 Power.org. All rights reserved.
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Version 1.1 – 7 March 2011 Power.org ePAPR
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LICENSE INFORMATION
© Copyright 2008,2011 Power.org, Inc
© Copyright Freescale Semiconductor, Inc., 2008,2011
© Copyright International Business Machines Corporation, 2008,2011
All Rights Reserved.
Version 1.1 – 7 March 2011 Power.org ePAPR
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Page 3 of 108
Table of Contents
REVISION HISTORY ................................................................................................................................... 7
1 INTRODUCTION .............................................................................................................................. 8
1.1 PURPOSE AND SCOPE ............................................................................................................................. 8
1.2 RELATIONSHIP TO IEEE™ 1275 ............................................................................................................. 10
1.3 32-BIT AND 64-BIT SUPPORT ................................................................................................................ 10
1.4 REFERENCES ....................................................................................................................................... 11
1.5 DEFINITION OF TERMS .......................................................................................................................... 13
2 THE DEVICE TREE .......................................................................................................................... 14
2.1 OVERVIEW ......................................................................................................................................... 14
2.2 DEVICE TREE STRUCTURE AND CONVENTIONS ........................................................................................... 15
2.2.1 Node Names ......................................................................................................................... 15
2.2.2 Generic Names Recommendation ........................................................................................ 17
2.2.3 Path Names .......................................................................................................................... 18
2.2.4 Properties .............................................................................................................................. 18
2.3 STANDARD PROPERTIES ........................................................................................................................ 21
2.3.1 compatible ............................................................................................................................ 21
2.3.2 model .................................................................................................................................... 21
2.3.3 phandle ................................................................................................................................. 22
2.3.4 status .................................................................................................................................... 23
2.3.5 #address-cells and #size-cells ............................................................................................... 24
2.3.6 reg ......................................................................................................................................... 25
2.3.7 virtual-reg ............................................................................................................................. 25
2.3.8 ranges ................................................................................................................................... 26
2.3.9 dma-ranges ........................................................................................................................... 28
2.3.10 name ................................................................................................................................ 29
2.3.11 device_type ...................................................................................................................... 29
2.4 INTERRUPTS AND INTERRUPT MAPPING ................................................................................................... 30
2.4.1 Properties for Interrupt Generating Devices ......................................................................... 32
2.4.2 Properties for Interrupt Controllers ...................................................................................... 33
2.4.3 Interrupt Nexus Properties .................................................................................................... 33
2.4.4 Interrupt Mapping Example .................................................................................................. 35
3 DEVICE NODE REQUIREMENTS ...................................................................................................... 37
3.1 BASE DEVICE NODE TYPES .................................................................................................................... 37
3.2 ROOT NODE ....................................................................................................................................... 37
3.3 ALIASES NODE ..................................................................................................................................... 38
3.4 MEMORY NODE .................................................................................................................................. 39
3.5 CHOSEN ............................................................................................................................................ 40
3.6 CPUS NODE PROPERTIES ..................................................................................................................... 41
3.7 CPU NODE PROPERTIES ....................................................................................................................... 41
3.7.1 General Properties of CPU nodes .......................................................................................... 42
3.7.2 TLB Properties ....................................................................................................................... 44
3.7.3 Internal (L1) Cache Properties .............................................................................................. 45
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3.7.4 Example ................................................................................................................................ 46
3.8 MULTI-LEVEL AND SHARED CACHES ........................................................................................................ 46
4 CLIENT PROGRAM IMAGE FORMAT .............................................................................................. 48
4.1 VARIABLE ADDRESS IMAGE FORMAT ....................................................................................................... 48
4.1.1 ELF Basics .............................................................................................................................. 48
4.1.2 Boot Program Requirements ................................................................................................ 48
4.1.3 Client Program Requirements ............................................................................................... 49
4.2 FIXED ADDRESS IMAGE FORMAT ............................................................................................................ 50
5 CLIENT PROGRAM BOOT REQUIREMENTS ..................................................................................... 51
5.1 BOOT AND SECONDARY CPUS ............................................................................................................... 51
5.2 DEVICE TREE ...................................................................................................................................... 51
5.3 INITIAL MAPPED AREAS ........................................................................................................................ 51
5.4 CPU ENTRY POINT REQUIREMENTS ........................................................................................................ 52
5.4.1 Boot CPU Initial Register State.............................................................................................. 52
5.4.2 I/O Devices State ................................................................................................................... 53
5.4.3 Initial I/O Mappings (IIO) ...................................................................................................... 53
5.4.4 Boot CPU Entry Requirements: Real Mode ........................................................................... 54
5.4.5 Boot CPU Entry Requirements for IMAs: Book IIII-E .............................................................. 54
5.5 SYMMETRIC MULTIPROCESSING (SMP) BOOT REQUIREMENTS .................................................................... 55
5.5.1 Overview ............................................................................................................................... 55
5.5.2 Spin Table ............................................................................................................................. 56
5.5.3 Implementation-Specific Release from Reset ....................................................................... 59
5.5.4 Timebase Synchronization .................................................................................................... 59
5.6 ASYMMETRIC CONFIGURATION CONSIDERATIONS ...................................................................................... 59
6 DEVICE BINDINGS ......................................................................................................................... 60
6.1 BINDING GUIDELINES ........................................................................................................................... 60
6.1.1 General Principles ................................................................................................................. 60
6.1.2 Miscellaneous Properties ...................................................................................................... 61
6.2 SERIAL DEVICES ................................................................................................................................... 62
6.2.1 Serial Class Binding ............................................................................................................... 62
6.2.2 National Semiconductor 16450/16550 Compatible UART Requirements ............................ 63
6.3 NETWORK DEVICES .............................................................................................................................. 63
6.3.1 Network Class Binding .......................................................................................................... 63
6.3.2 Ethernet specific considerations ........................................................................................... 64
6.4 OPEN PIC INTERRUPT CONTROLLERS ....................................................................................................... 66
6.5 SIMPLE-BUS ........................................................................................................................................ 66
7 VIRTUALIZATION ........................................................................................................................... 67
7.1 OVERVIEW ......................................................................................................................................... 67
7.2 HYPERCALL APPLICATION BINARY INTERFACE (ABI) ................................................................................... 67
7.3 EPAPR HYPERCALL TOKEN DEFINITION ................................................................................................... 68
7.4 HYPERCALL RETURN CODES ................................................................................................................... 69
7.5 HYPERVISOR NODE .............................................................................................................................. 70
7.6 EPAPR VIRTUAL INTERRUPT CONTROLLER SERVICES .................................................................................. 71
7.6.1 Virtual Interrupt Controller Device Tree Representation ...................................................... 71
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7.6.2 ePAPR Interrupt Controller Hypercalls .................................................................................. 73
7.7 BYTE-CHANNEL SERVICES ...................................................................................................................... 80
7.7.1 Overview ............................................................................................................................... 80
7.7.2 Interrupts and Guest Device Tree Representation ................................................................ 81
7.7.3 Byte-channel Hypercalls........................................................................................................ 82
7.8 INTER-PARTITION DOORBELLS ................................................................................................................ 84
7.8.1 Overview ............................................................................................................................... 84
7.8.2 Doorbell Send Endpoints ....................................................................................................... 84
7.8.3 Doorbell Receive Endpoints .................................................................................................. 84
7.8.4 Doorbell Hypercall ................................................................................................................ 85
7.9 MSGSND ............................................................................................................................................ 85
7.9.1 EV_MSGSND ......................................................................................................................... 85
7.10 IDLE ............................................................................................................................................. 86
EV_IDLE ............................................................................................................................................... 86
8 FLAT DEVICE TREE PHYSICAL STRUCTURE ...................................................................................... 87
8.1 VERSIONING ....................................................................................................................................... 87
8.2 HEADER ............................................................................................................................................ 88
8.3 MEMORY RESERVATION BLOCK.............................................................................................................. 89
8.3.1 Purpose ................................................................................................................................. 89
8.3.2 Format .................................................................................................................................. 90
8.4 STRUCTURE BLOCK .............................................................................................................................. 91
8.4.1 Lexical structure .................................................................................................................... 91
8.4.2 Tree structure ....................................................................................................................... 92
8.5 STRINGS BLOCK .................................................................................................................................. 93
8.6 ALIGNMENT ....................................................................................................................................... 94
APPENDIX A DEVICE TREE SOURCE FORMAT (VERSION 1) ..................................................................... 95
APPENDIX B1 EBONY DEVICE TREE ........................................................................................................ 97
APPENDIX B2 – MPC8572DS DEVICE TREE ............................................................................................ 104
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