ABSTRACT
ABSTRACT
With the rapid development of IT,the embedded devices of accessing to
Ethernet are used more and more widely.In order to make each device enjoy a
fair and effective shared communications medium, it is particularly important to
research the data processing system of the Ethernet MAC layer.
To this end,it is firstly done to analyze the basic connotation of Ethernet and
the related agreements,and to dissect the communication mechanisms of the
Ethernet MAC layer,the characteristics and format of the frame,the PHY
interface protocol,the ARP protocol,I
2
C protocol in the paper.According to the
characteristics and working principle of the FPGA chip ,the system design,
which supports the accessing of the 1000Base-T Ethernet,is determined based
on the combination of the 88E1111 PHY chip and XC3S400-4fg456C FPGA
chip of Xilinx.Then the hardware circuit design is accomplished by the Cadence
development tool.In this system, 88E1111 and FPGA respectively completes the
data processing of PHY layer and the data processing of the MAC layer,which
mainly consists of the calibration and dearchive of the receiving data frames, the
encapsulation of the data frames,the MAC address filtering, the extraction of the
IP packet,The ARP address mapping,and so on. So FPGA is the core of the
system. Following the top-down design conception,the design of FPGA
successively includes the top-level module,and the submodule of the PHY
interface,the MAC core processing,the user configuration,the user data
interface.
Keywords: Ethernet the MAC layer FPGA