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1. General description

The LPC1759/58/56/54/52/51 are ARM Cortex-M3 based microcontrollers for embedded

applications featuring a high level of integration and low power consumption. The ARM

Cortex-M3 is a next generation core that offers system enhancements such as enhanced

debug features and a higher level of support block integration.

The LPC1758/56/57/54/52/51 operate at CPU frequencies of up to 100 MHz. The

LPC1759 operates at CPU frequencies of up to 120 MHz. The ARM Cortex-M3 CPU

incorporates a 3-stage pipeline and uses a Harvard architecture with separate local

instruction and data buses as well as a third bus for peripherals. The ARM Cortex-M3

CPU also includes an internal prefetch unit that supports speculative branching.

The peripheral complement of the LPC1759/58/56/54/52/51 includes up to 512 kB of flash

memory, up to 64 kB of data memory, Ethernet MAC, USB Device/Host/OTG interface,

8-channel general purpose DMA controller, 4 UARTs, 2 CAN channels, 2 SSP controllers,

SPI interface, 2 I

C-bus interfaces, 2-input plus 2-output I

S-bus interface, 6 channel

12-bit ADC, 10-bit DAC, motor control PWM, Quadrature Encoder interface, 4 general

purpose timers, 6-output general purpose PWM, ultra-low power Real-Time Clock (RTC)

with separate battery supply, and up to 52 general purpose I/O pins.

2. Features and benefits

 ARM Cortex-M3 processor, running at frequencies of up to 100 MHz

(LPC1758/56/57/54/52/51) or of up to 120 MHz (LPC1759). A Memory Protection Unit

(MPU) supporting eight regions is included.

 ARM Cortex-M3 built-in Nested Vectored Interrupt Controller (NVIC).

 Up to 512 kB on-chip flash programming memory. Enhanced flash memory accelerator

enables high-speed 120 MHz operation with zero wait states.

 In-System Programming (ISP) and In-Application Programming (IAP) via on-chip

bootloader software.

 On-chip SRAM includes:

 Up to 32 kB of SRAM on the CPU with local code/data bus for high-performance

CPU access.

 Two/one 16 kB SRAM blocks with separate access paths for higher throughput.

These SRAM blocks may be used for Ethernet (LPC1758 only), USB, and DMA

memory, as well as for general purpose CPU instruction and data storage.

 Eight channel General Purpose DMA controller (GPDMA) on the AHB multilayer

matrix that can be used with the SSP, I

S-bus, UART, the Analog-to-Digital and

Digital-to-Analog converter peripherals, timer match signals, and for

memory-to-memory transfers.

LPC1759/58/56/54/52/51

32-bit ARM Cortex-M3 MCU; up to 512 kB flash and 64 kB

SRAM with Ethernet, USB 2.0 Host/Device/OTG, CAN

Rev. 6 — 25 August 2010 Product data sheet

Product data sheet Rev. 6 — 25 August 2010 2 of 73

NXP Semiconductors

LPC1759/58/56/54/52/51

32-bit ARM Cortex-M3 microcontroller

 Multilayer AHB matrix interconnect provides a separate bus for each AHB master.

AHB masters include the CPU, General Purpose DMA controller, Ethernet MAC

(LPC1758 only), and the USB interface. This interconnect provides communication

with no arbitration delays.

 Split APB bus allows high throughput with few stalls between the CPU and DMA.

 Serial interfaces:

 On the LPC1758 only, Ethernet MAC with RMII interface and dedicated DMA

controller.

 USB 2.0 full-speed device/Host/OTG controller with dedicated DMA controller and

on-chip PHY for device, Host, and OTG functions. The LPC1752/51 include a USB

device controller only.

 Four UARTs with fractional baud rate generation, internal FIFO, and DMA support.

One UART has modem control I/O and RS-485/EIA-485 support, and one UART

has IrDA support.

 CAN 2.0B controller with two (LPC1759/58/56) or one (LPC1754/52/51) channels.

 SPI controller with synchronous, serial, full duplex communication and

programmable data length.

 Two SSP controllers with FIFO and multi-protocol capabilities. The SSP interfaces

can be used with the GPDMA controller.

 Two I

C-bus interfaces supporting fast mode with a data rate of 400 kbit/s with

multiple address recognition and monitor mode.

 On the LPC1759/58/56 only, I

S (Inter-IC Sound) interface for digital audio input or

output, with fractional rate control. The I

S-bus interface can be used with the

GPDMA. The I

S-bus interface supports 3-wire and 4-wire data transmit and

receive as well as master clock input/output.

 Other peripherals:

 52 General Purpose I/O (GPIO) pins with configurable pull-up/down resistors. All

GPIOs support a new, configurable open-drain operating mode. The GPIO block is

accessed through the AHB multilayer bus for fast access and located in memory

such that it supports Cortex-M3 bit banding and use by the General Purpose DMA

Controller.

 12-bit Analog-to-Digital Converter (ADC) with input multiplexing among six pins,

conversion rates up to 200 kHz, and multiple result registers. The 12-bit ADC can

be used with the GPDMA controller.

 On the LPC1759/58/56/54 only, 10-bit Digital-to-Analog Converter (DAC) with

dedicated conversion timer and DMA support.

 Four general purpose timers/counters, with a total of three capture inputs and ten

compare outputs. Each timer block has an external count input. Specific timer

events can be selected to generate DMA requests.

 One motor control PWM with support for three-phase motor control.

 Quadrature encoder interface that can monitor one external quadrature encoder.

 One standard PWM/timer block with external count input.

 Real-Time Clock (RTC) with a separate power domain and dedicated RTC

oscillator. The RTC block includes 20 bytes of battery-powered backup registers.

 WatchDog Timer (WDT). The WDT can be clocked from the internal RC oscillator,

the RTC oscillator, or the APB clock.

 ARM Cortex-M3 system tick timer, including an external clock input option.

Product data sheet Rev. 6 — 25 August 2010 3 of 73

NXP Semiconductors

LPC1759/58/56/54/52/51

32-bit ARM Cortex-M3 microcontroller

 Repetitive Interrupt Timer (RIT) provides programmable and repeating timed

interrupts.

 Each peripheral has its own clock divider for further power savings.

 Standard JTAG test/debug interface for compatibility with existing tools. Serial Wire

Debug and Serial Wire Trace Port options.

 Emulation trace module enables non-intrusive, high-speed real-time tracing of

instruction execution.

 Integrated PMU (Power Management Unit) automatically adjusts internal regulators to

minimize power consumption during Sleep, Deep sleep, Power-down, and Deep

power-down modes.

 Four reduced power modes: Sleep, Deep-sleep, Power-down, and Deep power-down.

 Single 3.3 V power supply (2.4 V to 3.6 V).

 One external interrupt input configurable as edge/level sensitive. All pins on Port 0 and

Port 2 can be used as edge sensitive interrupt sources.

 Non-maskable Interrupt (NMI) input.

 The Wakeup Interrupt Controller (WIC) allows the CPU to automatically wake up from

any priority interrupt that can occur while the clocks are stopped in Deep sleep,

Power-down, and Deep power-down modes.

 Processor wake-up from Power-down mode via any interrupt able to operate during

Power-down mode (includes external interrupts, RTC interrupt, USB activity, Ethernet

wake-up interrupt (LPC1758 only), CAN bus activity, Port 0/2 pin interrupt, and NMI).

 Brownout detect with separate threshold for interrupt and forced reset.

 Power-On Reset (POR).

 Crystal oscillator with an operating range of 1 MHz to 25 MHz.

 4 MHz internal RC oscillator trimmed to 1 % accuracy that can optionally be used as a

system clock.

 PLL allows CPU operation up to the maximum CPU rate without the need for a

high-frequency crystal. May be run from the main oscillator, the internal RC oscillator,

or the RTC oscillator.

 USB PLL for added flexibility.

 Code Read Protection (CRP) with different security levels.

 Unique device serial number for identification purposes.

 Available as 80-pin LQFP package (12 mm ×

12 mm × 1.4 mm).

3. Applications

 eMetering

 Lighting

 Industrial networking

 Alarm systems

 White goods

 Motor control

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