ds21q59技术资料资源-CSDN文库

5星 · 超过95%的资源需积分: 12 45 浏览量 2009-02-14 13:22:24 上传评论收藏 652KB PDF 举报

资源推荐

资源详情

资源评论

1 of 76

REV: 090104

Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device

may be simultaneously available through various sales channels. For information about device errata, click here: www.maxim-ic.com/errata

GENERAL DESCRIPTION

The DS21Q59 E1 quad transceiver contains all the

necessary functions for connecting to four E1 lines.

The DS21Q59 is a direct replacement for the

DS21Q50, with the addition of signaling access and

improved interrupt handling. It is composed of a line

interface unit (LIU), framer, and a TDM backplane

interface, and is controlled through an 8-bit parallel

port configured for Intel or Motorola bus operations or

serial port operation.

APPLICATIONS

DSLAMs

Routers

IMA and WAN Equipment

PIN CONFIGURATION

FEATURES

§ Four Complete E1 (CEPT) PCM-30/ISDN-PRI

Transceivers

§ Pin Compatible with the DS21Q50

§ Long-Haul and Short-Haul Line Interfaces

§ 32-Bit or 128-Bit Crystal-Less Jitter Attenuator

§ Frames to FAS, CAS, and CRC4 Formats

§ CAS/CCS Signaling Support

§ 4MHz/8MHz/16MHz Clock Synthesizer

§ Flexible System Clock with Automatic Source

Switching on Loss-of-Clock Source

§ Two-Frame Elastic-Store Slip Buffer on the

Receive Side

§ Interleaving PCM Bus Operation Up to

16.384MHz

§ Configurable Parallel and Serial Port Operation

§ Detects and Generates Remote and AIS Alarms

§ Fully Independent Transmit and Receive

Functionality

§ Four Separate Loopback Functions

§ PRBS Generation/Detection/Error Counting

§ 3.3V Low-Power CMOS

§ Large Counters for Bipolar and Code Violations,

CRC4 Codeword Errors, FAS Word Errors, and

E Bits

§ Eight Additional User-Configurable Output Pins

§ 100-Pin (14mm) LQFP Package

ORDERING INFORMATION

PART TEMP RANGE PIN-PACKAGE

DS21Q59L 0°C to +70°C 100 LQFP

DS21Q59LN -40°C to +85°C 100 LQFP

LQFP

100

Dallas

Semiconducto

DS21Q59

TOP VIEW

DS21Q59

E1 Quad Transceive

www.maxim-ic.com

DS21Q59 Quad E1 Transceiver

2 of 76

TABLE OF CONTENTS

1. ACRONYMS .......................................................................................................................6

2. DETAILED DESCRIPTION.................................................................................................6

3. BLOCK DIAGRAM .............................................................................................................7

4. PIN DESCRIPTION.............................................................................................................8

4.1 PIN FUNCTION DESCRIPTIONS......................................................................................................12

5. FUNCTIONAL DESCRIPTION .........................................................................................13

6. HOST INTERFACE PORT................................................................................................14

6.1 PARALLEL PORT OPERATION .......................................................................................................14

6.2 SERIAL PORT OPERATION ............................................................................................................14

7. REGISTER MAP...............................................................................................................16

8. CONTROL, ID, AND TEST REGISTERS .........................................................................17

8.1 POWER-UP SEQUENCE................................................................................................................18

8.2 FRAMER LOOPBACK ....................................................................................................................21

8.3 AUTOMATIC ALARM GENERATION .................................................................................................22

8.4 REMOTE LOOPBACK ....................................................................................................................22

8.5 LOCAL LOOPBACK .......................................................................................................................23

9. STATUS AND INFORMATION REGISTERS ...................................................................27

9.1 INTERRUPT HANDLING .................................................................................................................28

9.2 CRC4 SYNC COUNTER................................................................................................................29

10. ERROR COUNT REGISTERS..........................................................................................34

10.1 BPV OR CV COUNTER .............................................................................................................34

10.2 CRC4 ERROR COUNTER..........................................................................................................34

10.3 E-BIT/PRBS BIT-ERROR COUNTER ..........................................................................................35

10.4 FAS ERROR COUNTER.............................................................................................................35

11. SIGNALING OPERATION................................................................................................36

11.1 RECEIVE SIGNALING.................................................................................................................36

11.2 TRANSMIT SIGNALING...............................................................................................................36

11.3 CAS OPERATION .....................................................................................................................36

12. DS0 MONITORING FUNCTION .......................................................................................37

13. PRBS GENERATION AND DETECTION.........................................................................39

14. SYSTEM CLOCK INTERFACE ........................................................................................40

15. TRANSMIT CLOCK SOURCE..........................................................................................41

16. IDLE CODE INSERTION ..................................................................................................41

DS21Q59 Quad E1 Transceiver

3 of 76

17. PER-CHANNEL LOOPBACK ..........................................................................................42

18. ELASTIC STORE OPERATION .......................................................................................42

19. ADDITIONAL (Sa) AND INTERNATIONAL (Si) BIT OPERATION..................................43

20. USER-CONFIGURABLE OUTPUTS................................................................................45

21. LINE INTERFACE UNIT ...................................................................................................47

21.1 RECEIVE CLOCK AND DATA RECOVERY .....................................................................................47

21.1.1 Termination ...........................................................................................................................................47

21.2 TRANSMIT WAVESHAPING AND LINE DRIVING .............................................................................48

21.3 JITTER ATTENUATORS ..............................................................................................................50

21.3.1 Clock and Data Jitter Attenuators .........................................................................................................50

21.3.2 Undedicated Clock Jitter Attenuator .....................................................................................................51

22. CODE MARK INVERSION (CMI) .....................................................................................52

23. INTERLEAVED PCM BUS OPERATION .........................................................................54

24. FUNCTIONAL TIMING DIAGRAMS.................................................................................56

24.1 RECEIVE..................................................................................................................................56

24.2 TRANSMIT................................................................................................................................58

25. OPERATING PARAMETERS...........................................................................................62

26. AC TIMING PARAMETERS AND DIAGRAMS ................................................................63

26.1 MULTIPLEXED BUS AC CHARACTERISTICS.................................................................................63

26.2 NONMULTIPLEXED BUS AC CHARACTERISTICS ..........................................................................66

26.3 SERIAL PORT ...........................................................................................................................68

26.4 RECEIVE AC CHARACTERISTICS ...............................................................................................69

26.5 TRANSMIT AC CHARACTERISTICS .............................................................................................72

26.6 SPECIAL MODES AC CHARACTERISTICS ....................................................................................74

27. PACKAGE INFORMATION..............................................................................................75

28. REVISION HISTORY........................................................................................................76

DS21Q59 Quad E1 Transceiver

4 of 76

LIST OF FIGURES

Figure 3-1. Block Diagram....................................................................................................................... 7

Figure 6-1. Serial Port Operation Mode 1 ...............................................................................................14

Figure 6-2. Serial Port Operation Mode 2 ...............................................................................................15

Figure 6-3. Serial Port Operation Mode 3 ...............................................................................................15

Figure 6-4. Serial Port Operation Mode 4 ...............................................................................................15

Figure 21-1. External Analog Connections (Basic Configuration) ...........................................................48

Figure 21-2. External Analog Connections (Protected Interface) ............................................................49

Figure 21-3. Transmit Waveform Template ............................................................................................50

Figure 21-4. Jitter Tolerance...................................................................................................................51

Figure 21-5. Jitter Attenuation ................................................................................................................51

Figure 22-1. CMI Coding ........................................................................................................................52

Figure 22-2. Example of CMI Code Violation (CV)..................................................................................53

Figure 23-1. IBO Configuration Using Two DS21Q59 Transceivers (Eight E1 Lines)..............................55

Figure 24-1. Receive Frame and Multiframe Timing ...............................................................................56

Figure 24-2. Receive Boundary Timing (With Elastic Store Disabled).....................................................56

Figure 24-3. Receive Boundary Timing (With Elastic Store Enabled) .....................................................56

Figure 24-4. Receive Interleave Bus Operation ......................................................................................57

Figure 24-5. Transmit Frame and Multiframe Timing ..............................................................................58

Figure 24-6. Transmit Boundary Timing..................................................................................................58

Figure 24-7. Transmit Interleave Bus Operation .....................................................................................59

Figure 24-8. Framer Synchronization Flowchart .....................................................................................60

Figure 24-9. Transmit Data Flow ............................................................................................................61

Figure 26-1. Intel Bus Read AC Timing (PBTS = 0)................................................................................64

Figure 26-2. Intel Bus Write Timing (PBTS = 0)......................................................................................64

Figure 26-3. Motorola Bus AC Timing (PBTS = 1) ..................................................................................65

Figure 26-4. Intel Bus Read Timing (PBTS = 0)......................................................................................66

Figure 26-5. Intel Bus Write Timing (PBTS = 0)......................................................................................67

Figure 26-6. Motorola Bus Read Timing (PBTS = 1)...............................................................................67

Figure 26-7. Motorola Bus Write Timing (PBTS = 1)...............................................................................67

Figure 26-8. Serial Bus Timing (BTS1 = 1, BTS0 = 0) ............................................................................68

Figure 26-9. Receive AC Timing (Receive Elastic Store Disabled) .........................................................70

Figure 26-10. Receive AC Timing (Receive Elastic Store Enabled)........................................................71

Figure 22-11. Transmit AC Timing (IBO Disabled)..................................................................................73

Figure 22-12. Transmit AC Timing (IBO Enabled) ..................................................................................74

Figure 26-13. NRZ Input AC Timing .......................................................................................................74

DS21Q59 Quad E1 Transceiver

5 of 76

LIST OF TABLES

Table 4-A. Pin Description (Sorted by Function)...................................................................................... 8

Table 4-B. Pin Assignments (Sorted by Number) ...................................................................................10

Table 4-C. System (Backplane) Interface Pins .......................................................................................12

Table 4-D. Alternate Jitter Attenuator .....................................................................................................12

Table 4-E. Clock Synthesizer .................................................................................................................12

Table 4-F. Parallel Port Control Pins ......................................................................................................12

Table 4-G. Serial Port Control Pins.........................................................................................................13

Table 4-H. Line Interface Pins ................................................................................................................13

Table 4-I. Supply Pins ............................................................................................................................13

Table 6-A. Bus Mode Select ...................................................................................................................14

Table 7-A. Register Map (Sorted by Address) ........................................................................................16

Table 8-A. Sync/Resync Criteria.............................................................................................................19

Table 8-B. G.703 Function......................................................................................................................24

Table 8-C. Output Modes .......................................................................................................................25

Table 9-A. Alarm Criteria ........................................................................................................................29

Table 13-A. Transmit PRBS Mode Select...............................................................................................39

Table 13-B. Receive PRBS Mode Select................................................................................................39

Table 14-A. Synthesizer Output Select...................................................................................................40

Table 14-B. System Clock Selection.......................................................................................................40

Table 20-A. OUTA and OUTB Function Select.......................................................................................46

Table 21-A. Line Build-Out Select in LICR..............................................................................................48

Table 21-B. Transformer Specifications..................................................................................................48

Table 23-A. IBO System Clock Select ....................................................................................................54

Table 23-B. IBO Device Assignment ......................................................................................................54

Table 26-A. AC Characteristics—Multiplexed Parallel Port.....................................................................63

Table 26-B. AC Characteristics—Nonmultiplexed Parallel Port ..............................................................66

Table 26-C. AC Characteristics—Serial Port (BTS1 = 1, BTS0 = 0) .......................................................68

Table 26-D. AC Characteristics—Receiver.............................................................................................69

Table 26-E. AC Characteristics—Transmit .............................................................................................72

Table 26-F. AC Characteristics—Special Modes ....................................................................................74

剩余75页未读，继续阅读

评论收藏

内容反馈

lifesky2006

2023-02-06

学习资料，借鉴参考
knowmuch

2013-01-21

该资源就是官网上的器件手册。
ima_zhan

2013-09-13

不错，有用处

renlei1029

粉丝: 3
资源: 4

ds21q59技术资料

单片四路E1收发器DS21Q59及其应用

DS90UR241Q资料

XK3190-DS3耀华称重仪表说明书含通信协议

谷氨酸棒杆菌DS酶的基因克隆及L183Q定点突变

安防天下智能网络视频监控技术详解与实践part2

安防天下智能网络视频监控技术详解与实践.part3

以太网协议栈芯片 CH395DS1技术手册-综合文档

利用哈希查找链地址法查找元素

STM32F407单片机开发板PDF原理图+AD集成封装库+主要器件技术手册资料.zip

DS1302电子时钟 LCD1602显示 电子万年历（DIY006）-电路方案

安防天下智能网络视频监控技术详解与实践part1

STM32F767单片机核心板+开发底板PDF原理图+AD集成封装库+主要器件技术手册.zip

ALIENTEK STM32H750核心板底板 PDF原理图+AD集成封装库+主要器件技术手册.zip

低功耗单键单感应通道触摸芯片VKD223B,多用于TWS/触摸夜灯/镜灯等，技术资料

数据结构实验报告(2).doc

STM32F103单片机开发板PDF原理图+ALTIUM集成封装库+芯片技术手册.zip

STM32F407单片机开发板PDF原理图+器件AD集成封装库+主要器件技术手册.zip

IP交换技术协议与体系结构

三菱运动CPU的应用.rar

计算机通信交换技术

解决Win 10与不兼容VirtualBox操作过程文档+（附带软件）.zip

计算机网络知识点总结(谢希仁第八版).pdf

Xshell软件(配色方案&amp;高亮关键字/突出显示集)的相关文件

湖南科技大学《计算机网络》配套课件（PDF版）

《计算机网络自顶向下方法第7版》中文PDF+复习题问题中文版答案

计算机网络自顶向下方法第八版答案

H3C-iNode-PC-7.3-E0630

hevc视频扩展免费2.0.53348.0x64

quickping下载

最新资源

DS1302电子时钟 LCD1602显示电子万年历（DIY006）-电路方案

Xshell软件(配色方案&高亮关键字/突出显示集)的相关文件