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IR2125-芯片资料介绍.pdf
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IR2125-芯片资料介绍.pdf
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Features
• Floating channel designed for bootstrap operation
Fully operational to +500V
Tolerant to negative transient voltage
dV/dt immune
• Gate drive supply range from 12 to 18V
• Undervoltage lockout
• Current detection and limiting loop to limit driven
power transistor current
• Error lead indicates fault conditions and programs
shutdown time
• Output in phase with input
• 2.5V, 5V and 15V input logic compatible
Description
The IR2125(S) is a high voltage, high speed power
MOSFET and IGBT driver with over-current limiting
protection circuitry. Proprietary HVIC and latch im-
mune CMOS technologies enable ruggedized mono-
lithic construction. Logic inputs are compatible with
standard CMOS or LSTTL outputs, down to 2.5V
logic. The output driver features a high pulse current
buffer stage designed for minimum driver cross-
CURRENT LIMITING SINGLE CHANNEL DRIVER
Product Summary
V
OFFSET
500V max.
I
O
+/- 1A / 2A
V
OUT
12 - 18V
V
CSth
230 mV
t
on/off
(typ.) 150 & 150 ns
Packages
Typical Connection
conduction. The protection circuitry detects over-current in the driven power transistor and limits the gate drive volt-
age. Cycle by cycle shutdown is programmed by an external capacitor which directly controls the time interval
between detection of the over-current limiting conditions and latched shutdown. The floating channel can be used to
drive an N-channel power MOSFET or IGBT in the high or low side configuration which operates up to 500 volts.
V
CC
V
B
CS
OUT
V
S
COM
IN
ERR
V
CC
IN
TO
LOAD
up to 500V
IR2125
(
S
)
Data Sheet No. PD60017-M
www.irf.com 1
(Refer to Lead Assignments for correct pin configuration). This/These diagram(s) show electrical
connections only. Please refer to our Application Notes and DesignTips for proper circuit board layout.
8-Lead PDIP
16-Lead SOIC
(Wide Body)
IR2125
(
S
)
2 www.irf.com
Symbol Definition Min. Max. Units
V
B
High Side Floating Supply Voltage -0.3 525
V
S
High Side Floating Offset Voltage V
B
- 25 V
B
+ 0.3
V
HO
High Side Floating Output Voltage V
S
- 0.3 V
B
+ 0.3
V
CC
Logic Supply Voltage -0.3 25 V
V
IN
Logic Input Voltage -0.3 V
CC
+ 0.3
V
ERR
Error Signal Voltage -0.3 V
CC
+ 0.3
V
CS
Current Sense Voltage V
S
- 0.3 V
B
+ 0.3
dV
s
/dt Allowable Offset Supply Voltage Transient — 50 V/ns
P
D
Package Power Dissipation @ T
A
≤ +25°C (8 lead PDIP) — 1.0
(16 lead SOIC) — 1.25
Rth
JA
Thermal Resistance, Junction to Ambient (8 lead PDIP) — 125
(16lLead SOIC) — 100
T
J
Junction Temperature — 150
T
S
Storage Temperature -55 150
T
L
Lead Temperature (Soldering, 10 seconds) — 300
Absolute Maximum Ratings
Absolute Maximum Ratings indicate sustained limits beyond which damage to the device may occur. All voltage param-
eters are absolute voltages referenced to COM. The Thermal Resistance and Power Dissipation ratings are measured
under board mounted and still air conditions.
Symbol Definition Min. Max. Units
V
B
High Side Floating Supply Voltage V
S
+ 12 V
S
+ 18
V
S
High Side Floating Offset Voltage Note 1 500
V
HO
High Side Floating Output Voltage V
S
V
B
V
CC
Logic Supply Voltage 0 18
V
IN
Logic Input Voltage 0 V
CC
V
ERR
Error Signal Voltage 0 V
CC
V
CS
Current Sense Signal Voltage V
S
V
B
T
A
Ambient Temperature -40 125 °C
Note 1: Logic operational for V
S
of -5 to +500V. Logic state held for V
S
of -5V to -V
BS
. (Please refer to the Design Tip
DT97-3 for more details).
Recommended Operating Conditions
The Input/Output logic timing diagram is shown in Figure 1. For proper operation the device should be used within the
recommended conditions. The V
S
offset rating is tested with all supplies biased at 15V differential.
W
°C/W
°C
V
www.irf.com 3
IR2125
(
S
)
Symbol Definition Figure Min. Typ. Max. Units Test Conditions
V
IH
Logic “1” Input Voltage 14 2.2 — —
V
IL
Logic “0” Input Voltage 15 — — 0.8
V
CSTH+
CS Input Positive Going Threshold 16 150 230 320
V
CSTH-
CS Input Negative Going Threshold 17 130 200 260
V
OH
High Level Output Voltage, V
BIAS
- V
O
18 — — 100 I
O
= 0A
V
OL
Low Level Output Voltage, V
O
19 — — 100 I
O
= 0A
I
LK
Offset Supply Leakage Current 20 — — 50 V
B
= V
S
= 500V
I
QBS
Quiescent V
BS
Supply Current 21 — 400 1000 V
IN
= V
CS
= 0V or 5V
I
QCC
Quiescent V
CC
Supply Current 22 — 700 1200 V
IN
= V
CS
= 0V or 5V
I
IN+
Logic “1” Input Bias Current 23 — 4.5 10 µA V
IN
= 5V
I
IN-
Logic “0” Input Bias Current 24 — — 1.0 V
IN
= 0V
I
CS+
“High” CS Bias Current 25 — 4.5 10 V
CS
= 3V
I
CS-
“Low” CS Bias Current 26 — — 1.0 V
CS
= 0V
V
BSUV+
V
BS
Supply Undervoltage Positive Going 27 8.5 9.2 10.0
Threshold
V
BSUV-
V
BS
Supply Undervoltage Negative Going 28 7.7 8.3 9.0
Threshold
V
CCUV+
V
CC
Supply Undervoltage Positive Going 29 8.3 8.9 9.6
Threshold
V
CCUV-
V
CC
Supply Undervoltage Negative Going 30 7.3 8.0 8.7
Threshold
I
ERR
ERR Timing Charge Current 31 65 100 130 V
IN
= 5V, V
CS
= 3V
ERR < V
ERR+
I
ERR+
ERR Pull-Up Current 32 8.0 15 — V
IN
= 5V, V
CS
= 3V
ERR > V
ERR+
I
ERR-
ERR Pull-Down Current 33 16 30 — V
IN
= 0V
I
O+
Output High Short Circuit Pulsed Current 34 1.0 1.6 — V
O
= 0V, V
IN
= 5V
PW ≤ 10 µs
I
O-
Output Low Short Circuit Pulsed Current 35 2.0 3.3 — V
O
= 15V, V
IN
= 0V
PW ≤ 10 µs
V
mV
mA
V
µA
A
Static Electrical Characteristics
V
BIAS
(V
CC
, V
BS
) = 15V and T
A
= 25°C unless otherwise specified. The V
IN
, V
TH
and I
IN
parameters are referenced to
COM. The V
O
and I
O
parameters are referenced to V
S
.
Dynamic Electrical Characteristics
V
BIAS
(V
CC
, V
BS
) = 15V, C
L
= 3300 pF and T
A
= 25°C unless otherwise specified. The dynamic electrical characteristics
are measured using the test circuit shown in Figures 3 through 6.
Symbol Definition Figure Min. Typ. Max. Units Test Conditions
t
on
Turn-On Propagation Delay 7 — 150 200 V
IN
= 0 & 5V
V
S
= 0 to 600V
t
off
Turn-Off Propagation Delay 8 — 150 190
t
sd
ERR Shutdown Propagation Delay 9 — 1.7 2.2 µs
t
r
Turn-On Rise Time 10 — 43 60
t
f
Turn-Off Fall Time 11 — 26 35
t
cs
CS Shutdown Propagation Delay 12 — 0.7 1.2
t
err
CS to ERR Pull-Up Propagation Delay 13 — 9.0 12 C
ERR
= 270 pF
ns
µs
ns
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