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 2003 Microchip Technology Inc. DS21117A-page 1

MCP6S21/2/6/8

Features

• Multiplexed Inputs: 1, 2, 6 or 8 channels

• 8 Gain Selections:

- +1, +2, +4, +5, +8, +10, +16 or +32 V/V

• Serial Peripheral Interface (SPI™)

• Rail-to-Rail Input and Output

• Low Gain Error: ±1% (max)

• Low Offset: ±275 µV (max)

• High Bandwidth: 2 to 12 MHz (typ)

• Low Noise: 10 nV/√Hz @ 10 kHz (typ)

• Low Supply Current: 1.0 mA (typ)

• Single Supply: 2.5V to 5.5V

Typical Applications

• A/D Converter Driver

• Multiplexed Analog Applications

• Data Acquisition

• Industrial Instrumentation

• Test Equipment

• Medical Instrumentation

Package Types

Description

The Microchip Technology Inc. MCP6S21/2/6/8 are

analog Programmable Gain Amplifiers (PGA). They

can be configured for gains from +1 V/V to +32 V/V and

the input multiplexer can select one of up to eight chan-

nels through an SPI port. The serial interface can also

put the PGA into shutdown to conserve power. These

PGAs are optimized for high speed, low offset voltage

and single-supply operation with rail-to-rail input and

output capability. These specifications support single

supply applications needing flexible performance or

multiple inputs.

The one channel MCP6S21 and the two channel

MCP6S22 are available in 8-pin PDIP, SOIC and

MSOP packages. The six channel MCP6S26 is avail-

able in 14-pin PDIP, SOIC and TSSOP packages. The

eight channel MCP6S28 is available in 16-pin PDIP

and SOIC packages. All parts are fully specified from

-40°C to +85°C.

Block Diagram

REF

CH0

SCK

OUT

CH1

CH0

CH2

REF

OUT

CH3

SCK

CH5

CH4

CH0

OUT

CH1

13 SI

SCK

CH2

CH4

CH7

CH5

CH6

CH3

CH1

CH0

SCK

OUT

MCP6S21

PDIP, SOIC, MSOP

MCP6S26

PDIP, SOIC, TSSOP

MCP6S28

PDIP, SOIC

MCP6S22

PDIP, SOIC, MSOP

REF

OUT

REF

SCK

CH1

CH0

CH3

CH2

CH5

CH4

CH7

CH6

MUX

SPI™

Logic

POR

Gain

Switches

Resistor Ladder (R

LAD

)

Single-Ended, Rail-to-Rail I/O, Low Gain PGA

MCP6S21/2/6/8

DS21117A-page 2  2003 Microchip Technology Inc.

1.0 ELECTRICAL

CHARACTERISTICS

Absolute Maximum Ratings †

- V

.........................................................................7.0V

All inputs and outputs....................... V

- 0.3V to V

+0.3V

Difference Input voltage ........................................ |V

- V

Output Short Circuit Current...................................continuous

Current at Input Pin .............................................................±2mA

Current at Output and Supply Pins ................................ ±30 mA

Storage temperature .....................................-65°C to +150°C

Junction temperature .................................................. +150°C

ESD protection on all pins (HBM;MM).................. ≥ 2 kV; 200V

† Notice: Stresses above those listed under "Maximum

Ratings" may cause permanent damage to the device. This is

a stress rating only and functional operation of the device at

those or any other conditions above those indicated in the

operation listings of this specification is not implied. Exposure

to maximum rating conditions for extended periods may affect

device reliability.

PIN FUNCTION TABLE

Name Function

OUT

Analog Output

CH0-CH7 Analog Inputs

Negative Power Supply

Positive Power Supply

SCK SPI Clock Input

SI SPI Serial Data Input

SO SPI Serial Data Output

SPI Chip Select

REF

External Reference Pin

DC CHARACTERISTICS

Electrical Specifications: Unless otherwise indicated, T

=+25°C, V

= +2.5V to +5.5V, V

= GND, V

REF

= V

, G = +1 V/V,

Input = CH0 = (0.3V)/G, CH1 to CH7 = 0.3V, R

=10kΩ to V

/2, SI and SCK are tied low and CS is tied high.

Parameters Sym Min Typ Max Units Conditions

Amplifier Input

Input Offset Voltage V

-275 — +275 µV G = +1, V

= 4.0V

Input Offset Voltage Drift ∆V

/∆T

—±4 —µV/°CT

= -40 to +85°C

Power Supply Rejection Ratio PSRR 70 85 — dB G = +1 (Note 1)

Input Bias Current I

— ±1 — pA CHx = V

Input Bias Current over

Temperature

— — 250 pA T

= -40 to +85°C,

CHx = V

Input Impedance Z

—10

||15 — Ω||pF

Input Voltage Range V

IVR

−0.3 — V

+0.3 V

Amplifier Gain

Nominal Gains G — 1 to 32 — V/V +1, +2, +4, +5, +8, +10, +16 or +32

DC Gain Error G = +1 g

-0.1 — +0.1 % V

OUT

≈ 0.3V to V

− 0.3V

G ≥ +2 g

-1.0 — +1.0 % V

OUT

≈ 0.3V to V

− 0.3V

DC Gain Drift G = +1 ∆G/∆T

— ±0.0002 — %/°C T

= -40 to +85°C

G ≥ +2 ∆G/∆T

— ±0.0004 — %/°C T

= -40 to +85°C

Internal Resistance R

LAD

3.4 4.9 6.4 kΩ (Note 1)

Internal Resistance over

Temperature

∆R

LAD

/∆T

—+0.028 — %/°C(Note 1)

= -40 to +85°C

Amplifier Output

DC Output Non-linearity G = +1 V

ONL

— ±0.003 — % of FSR V

OUT

= 0.3V to V

− 0.3V, V

= 5.0V

G ≥ +2 V

ONL

— ±0.001 — % of FSR V

OUT

= 0.3V to V

− 0.3V, V

= 5.0V

Maximum Output Voltage Swing V

, V

+20 — V

-100 mV G ≥ +2; 0.5V output overdrive

+60 — V

-60 G ≥ +2; 0.5V output overdrive,

REF

= V

Short-Circuit Current I

O(SC)

—±30 — mA

Note 1: R

LAD

+ R

in Figure 4-1) connects V

REF

, V

OUT

and the inverting input of the internal amplifier. The MCP6S22 has

REF

tied internally to V

, so V

is coupled to the internal amplifier and the PSRR spec describes PSRR+ only. We

recommend the MCP6S22’s V

pin be tied directly to ground to avoid noise problems.

2: I

includes current in R

LAD

(typically 60 µA at V

OUT

= 0.3V). Both I

and I

Q_SHDN

exclude digital switching currents.

3: The output goes Hi-Z and the registers reset to their defaults; see Section 5.4, “Power-On Reset”.

 2003 Microchip Technology Inc. DS21117A-page 3

MCP6S21/2/6/8

Power Supply

Supply Voltage V

2.5 — 5.5 V

Quiescent Current I

0.5 1.0 1.35 mA I

= 0 (Note 2)

Quiescent Current, Shutdown

mode

Q_SHDN

—0.51.0 µAI

= 0 (Note 2)

Power-On Reset

POR Trip Voltage V

POR

1.2 1.7 2.2 V (Note 3)

POR Trip Voltage Drift ∆V

POR

/∆T— -3.0 — mV/°CT

= -40°C to+85°C

DC CHARACTERISTICS (CONTINUED)

Electrical Specifications: Unless otherwise indicated, T

=+25°C, V

= +2.5V to +5.5V, V

= GND, V

REF

= V

, G = +1 V/V,

Input = CH0 = (0.3V)/G, CH1 to CH7 = 0.3V, R

=10kΩ to V

/2, SI and SCK are tied low and CS is tied high.

Parameters Sym Min Typ Max Units Conditions

Note 1: R

LAD

+ R

in Figure 4-1) connects V

REF

, V

OUT

and the inverting input of the internal amplifier. The MCP6S22 has

REF

tied internally to V

, so V

is coupled to the internal amplifier and the PSRR spec describes PSRR+ only. We

recommend the MCP6S22’s V

pin be tied directly to ground to avoid noise problems.

2: I

includes current in R

LAD

(typically 60 µA at V

OUT

= 0.3V). Both I

and I

Q_SHDN

exclude digital switching currents.

3: The output goes Hi-Z and the registers reset to their defaults; see Section 5.4, “Power-On Reset”.

AC CHARACTERISTICS

Electrical Specifications: Unless otherwise indicated, T

=+25°C, V

= +2.5V to +5.5V, V

= GND, V

REF

= V

, G = +1 V/V,

Input = CH0 =(0.3V)/G, CH1 to CH7=0.3V, R

=10kΩ to V

/2, C

= 60 pF, SI and SCK are tied low, and CS is tied high.

Parameters Sym Min Typ Max Units Conditions

Frequency Response

-3 dB Bandwidth BW — 2 to 12 — MHz All gains; V

OUT

< 100 mV

P-P

(Note 1)

Gain Peaking GPK — 0 — dB All gains; V

OUT

< 100 mV

P-P

Total Harmonic Distortion plus Noise

f = 1 kHz, G = +1 V/V THD+N — 0.0015 — %

OUT

= 1.5V ± 1.0V

, V

= 5.0V,

BW = 22 kHz

f = 1 kHz, G = +4 V/V THD+N — 0.0058 — %

OUT

= 1.5V ± 1.0V

, V

= 5.0V,

BW = 22 kHz

f = 1 kHz, G = +16 V/V THD+N — 0.023 — %

OUT

= 1.5V ± 1.0V

, V

= 5.0V,

BW = 22 kHz

f = 20 kHz, G = +1 V/V THD+N — 0.0035 — %

OUT

= 1.5V ± 1.0V

, V

= 5.0V,

BW = 80 kHz

f = 20 kHz, G = +4 V/V THD+N — 0.0093 — %

OUT

= 1.5V ± 1.0V

, V

= 5.0V,

BW = 80 kHz

f = 20 kHz, G = +16 V/V THD+N — 0.036 — %

OUT

= 1.5V ± 1.0V

, V

= 5.0V,

BW = 80 kHz

Step Response

Slew Rate SR — 4.0 — V/µs G = 1, 2

— 11 — V/µs G = 4, 5, 8, 10

—22—V/µsG = 16, 32

Noise

Input Noise Voltage E

—3.2—µV

P-P

f = 0.1 Hz to 10 kHz (Note 2)

— 26 — f = 0.1 Hz to 200 kHz (Note 2)

Input Noise Voltage Density e

—10—nV/√Hz f = 10 kHz (Note 2)

Input Noise Current Density i

—4—fA/√Hz f = 10 kHz

Note 1: See Table 4-1 for a list of typical numbers.

2: E

and e

include ladder resistance noise. See Figure 2-33 for e

vs. G data.

MCP6S21/2/6/8

DS21117A-page 4  2003 Microchip Technology Inc.

DIGITAL CHARACTERISTICS

Electrical Specifications: Unless otherwise indicated, T

=+25°C, V

= +2.5V to +5.5V, V

= GND, V

REF

= V

, G = +1 V/V,

Input = CH0 = (0.3V)/G, CH1 to CH7 = 0.3V, R

=10kΩ to V

/2, C

= 60 pF, SI and SCK are tied low, and CS is tied high.

Parameters Sym Min Typ Max Units Conditions

SPI Inputs (CS

, SI, SCK)

Logic Threshold, Low V

0 — 0.3V

Input Leakage Current I

-1.0 — +1.0 µA

Logic Threshold, High V

0.7V

—V

Amplifier Output Leakage Current — -1.0 — +1.0 µA In Shutdown mode

SPI Output (SO, for MCP6S26 and MCP6S28)

Logic Threshold, Low V

—V

+0.4 V I

= 2.1 mA, V

= 5V

Logic Threshold, High V

-0.5 — V

= -400 µA

SPI Timing

Pin Capacitance C

— 10 — pF All digital I/O pins

Input Rise/Fall Times (CS

, SI, SCK)

RFI

——2µsNote 1

Output Rise/Fall Times (SO) t

RFO

— 5 — ns MCP6S26 and MCP6S28

high time

CSH

40 — — ns

SCK edge to CS

fall setup time

CS0

10 — — ns

SCK edge when CS is high

fall to first SCK edge setup time

CSSC

40 — — ns

SCK Frequency f

SCK

——10MHzV

= 5V (Note 2)

SCK high time t

40 — — ns

SCK low time t

40 — — ns

SCK last edge to CS

rise setup time

SCCS

30 — — ns

rise to SCK edge setup time

CS1

100 — — ns

SCK edge when CS is high

SI set-up time t

40 — — ns

SI hold time t

10 — — ns

SCK to SO valid propagation delay t

— — 80 ns MCP6S26 and MCP6S28

rise to SO forced to zero

SOZ

— — 80 ns MCP6S26 and MCP6S28

Channel and Gain Select Timing

Channel Select Time t

— 1.5 — µs CHx = 0.6V, CHy =0.3V, G = 1,

CHx to CHy select

S = 0.7V

to V

OUT

90% point

Gain Select Time t

— 1 — µs CHx = 0.3V, G = 5 to G = 1 select,

S = 0.7V

to V

OUT

90% point

Shutdown Mode Timing

Out of Shutdown mode (CS

goes

high) to Amplifier Output Turn-on

Time

—3.510µs

= 0.7V

to V

OUT

90% point

Into Shutdown mode (CS

goes high)

to Amplifier Output High-Z Turn-off

Time

OFF

—1.5—µs

= 0.7V

to V

OUT

90% point

POR Timing

Power-On Reset power-up time t

RPU

—30—µsV

= V

POR

- 0.1V to V

POR

+ 0.1V,

50% V

to 90% V

OUT

point

Power-On Reset power-down time t

RPD

—10—µsV

= V

POR

+ 0.1V to V

POR

- 0.1V,

50% V

to 90% V

OUT

point

Note 1: Not tested in production. Set by design and characterization.

2: When using the device in the daisy chain configuration, maximum clock frequency is determined by a combination of

propagation delay time (t

≤ 80 ns), data input setup time (t

≥ 40 ns), SCK high time (t

≥ 40 ns), and SCK rise and

fall times of 5 ns. Maximum f

SCK

is, therefore, ≈ 5.8 MHz.

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