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xilinx原语相关介绍最新版(ug974)

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UltraScale Architecture

Libraries Guide

UG974 (v2023.1) May 10, 2023

See all versions

of this document

AMD Adaptive Computing is creating an environment where

employees, customers, and partners feel welcome and included. To

that end, we’re removing non-inclusive language from our products

and related collateral. We’ve launched an internal initiative to remove

language that could exclude people or reinforce historical biases,

including terms embedded in our software and IPs. You may still find

examples of non-inclusive language in our older products as we work

to make these changes and align with evolving industry standards.

Follow this link for more information.

Chapter 1

Introduction

Overview

This HDL guide is part of the AMD Vivado™ Design Suite documentaon collecon.

This guide contains the following:

•

Introducon

•

Descripons of each available macro

•

A list of design elements supported in this architecture, organized by funconal categories

• Descripons of each available primive

About Design Elements

This version of the Libraries Guide describes the valid design elements for AMD UltraScale™

architecture-based devices including the AMD UltraScale™ and AMD UltraScale+™ families, and

includes examples of instanaon code for each element. Instanaon templates are also

supplied in a separate ZIP le, which you can nd on www.xilinx.com linked to this le or within

the Language Templates in the Vivado Design Suite.

Design elements are divided into the following main categories:

• Macros: These elements are in the Xilinx Parameterized Macro library in the tool, and are used

to instanate elements that are complex to instanate by just using the primives. The

synthesis tools will automacally expand the macros to their underlying primives.

IMPORTANT! Unimacros from previous generaon AMD FPGA architectures are not supported in the

UltraScale architecture and have been replaced by Xilinx Parameterized Macros.

• Primives: Components that are nave to the architecture you are targeng.

Design Entry Methods

For each design element in this guide, AMD evaluates the opons for using the design element,

and recommends what we believe is the best soluon for you. The opons are:

• Instanaon: This component can be instanated directly into the design. This method is

useful if you want to control the exact use, implementaon, or placement of the individual

blocks.

Chapter 1: Introduction

UG974 (v2023.1) May 10, 2023

UltraScale Architecture Libraries Guide 2

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• Inference: This component can be inferred by most supported synthesis tools. You should use

this method if you want to have complete exibility and portability of the code to mulple

architectures. Inference also gives the tools the ability to opmize for performance, area, or

power, as specied by the user to the synthesis tool.

• IP and IP Integrator Catalog: This component can be instanated from the IP catalog. The IP

catalog maintains a library of IP Cores assembled from mulple primives to form more

complex funcons, as well as interfaces to help in instanaon of the more complex

primives. References here to the IP catalog generally refer to the laer, where you use the IP

catalog to assist in the use and integraon of certain primives into your design.

Navigating Content by Design Process

AMD Adapve Compung documentaon is organized around a set of standard design

processes to help you nd relevant content for your current development task. All AMD Versal™

adapve SoC design process Design Hubs and the Design Flow Assistant materials can be found

on the Xilinx.com website. This document covers the following design processes:

• Hardware, IP, and Plaorm Development: Creang the PL IP blocks for the hardware

plaorm, creang PL kernels, funconal simulaon, and evaluang the AMD Vivado™ ming,

resource use, and power closure. Also involves developing the hardware plaorm for system

integraon.

Chapter 1: Introduction

UG974 (v2023.1) May 10, 2023

UltraScale Architecture Libraries Guide 3

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Chapter 2

Xilinx Parameterized Macros

About Xilinx Parameterized Macros

This secon describes Xilinx Parameterized Macros that can be used with UltraScale™

architecture-based devices. The macros are organized alphabecally.

IMPORTANT! Unimacros from previous generaon AMD FPGA architectures are not supported in the

UltraScale architecture and have been replaced by Xilinx Parameterized Macros.

The following informaon is provided for each macro, where applicable:

• Name, descripon, macro group, macro subgroup, and family

• Schemac symbol

• Introducon

• Logic diagram (if any)

• Port descripons

• Design Entry Method

• Available aributes

• Example instanaon templates

• Links to addional informaon

Enabling Xilinx Parameterized Macros

The following instrucons describe how to prepare Vivado to use the XPM libraries.

1. Ensure Vivado can idenfy the XPMs.

• When using the IDE and/or the project ow, the tools will parse the les added to the

project and setup Vivado to recognize the XPMs.

• When using the non-project ow, you must issue the auto_detect_xpm command.

Select the XPM template that you wish to use from below.

Copy the contents of the template and paste into your own source le.

Set parameters/generics, and wire ports according to the documentaon provided as code

comments.

Note: Be sure to read and comply with all code comments to properly use the XPMs.

Chapter 2: Xilinx Parameterized Macros

UG974 (v2023.1) May 10, 2023

UltraScale Architecture Libraries Guide 4

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Testbench

A testbench for XPM CDC macros is available in the XPM CDC Testbench File.

A testbench for XPM FIFO macros is available in the XPM FIFO Testbench File.

Instantiation Templates

Instanaon templates for Xilinx Parameterized Macros are also available in Vivado, as well as in

a downloadable ZIP le. Because PDF includes headers and footers if you copy text that spans

pages, you should copy templates from Vivado or the downloaded ZIP le whenever possible.

Instanaon templates can be found on the Web in the Instanaon Templates for Xilinx

Parameterizable Macros le.

List of Xilinx Parameterized Macros

XPM_CDC_ARRAY_SINGLE Parameterized Macro: Single-bit Array Synchronizer CDC

XPM_CDC_ASYNC_RST Parameterized Macro: Asynchronous Reset Synchronizer CDC

XPM_CDC_GRAY Parameterized Macro: Synchronizer via Gray Encoding CDC

XPM_CDC_HANDSHAKE Parameterized Macro: Bus Synchronizer with Full

Handshake

CDC

XPM_CDC_PULSE Parameterized Macro: Pulse Transfer CDC

XPM_CDC_SINGLE Parameterized Macro: Single-bit Synchronizer CDC

XPM_CDC_SYNC_RST Parameterized Macro: Synchronous Reset Synchronizer CDC

XPM_FIFO_ASYNC Parameterized Macro: Asynchronous FIFO FIFO

XPM_FIFO_AXIF Parameterized Macro: AXI-Full FIFO FIFO

XPM_FIFO_AXIL Parameterized Macro: AXI-Lite FIFO FIFO

XPM_FIFO_AXIS Parameterized Macro: AXI Stream FIFO FIFO

XPM_FIFO_SYNC Parameterized Macro: Synchronous FIFO FIFO

XPM_MEMORY_DPDISTRAM Parameterized Macro: Dual Port Distributed RAM Memory

XPM_MEMORY_DPROM Parameterized Macro: Dual Port ROM Memory

XPM_MEMORY_SDPRAM Parameterized Macro: Simple Dual Port RAM Memory

XPM_MEMORY_SPRAM Parameterized Macro: Single Port RAM Memory

XPM_MEMORY_SPROM Parameterized Macro: Single Port ROM Memory

XPM_MEMORY_TDPRAM Parameterized Macro: True Dual Port RAM Memory

Chapter 2: Xilinx Parameterized Macros

UG974 (v2023.1) May 10, 2023

UltraScale Architecture Libraries Guide 5

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