ADF41513数据手册.PDF资源-CSDN文库

需积分: 50 179 浏览量 2022-03-17 10:52:08 上传评论收藏 1.36MB PDF 举报

资源详情

资源评论

26.5 GHz, Integer N/Fractional-N,

PLL Synthesizer

Data Sheet

ADF41513

Rev. 0 Document Feedback

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Technical Support www.analog.com

FEATURES

1 GHz to 26.5 GHz bandwidth

Ultralow noise PLL

Integer N = −235 dBc/Hz, fractional-N = −231 dBc/Hz

High maximum PFD frequency

Integer N = 250 MHz, fractional-N = 125 MHz

25-bit fixed/49-bit variable fractional modulus mode

Single-ended reference input

3.3 V power supply, 3.3 V charge pump

Integrated 1.8 V logic capability

Phase resync

Programmable charge pump currents: 16× range

Digital lock detect

3-wire serial interface with register readback option

Hardware and software power-down mode

Operating range from −40°C to +105°C

APPLICATIONS

Test equipment and instrumentation

Wireless infrastructure

Microwave point to point and multipoint radios

Very small aperture terminal (VSAT ) radios

Aerospace and defense

GENERAL DESCRIPTION

The ADF41513 is an ultralow noise frequency synthesizer that

can be used to implement local oscillators (LOs) as high as

26.5 GHz in the upconversion and downconversion sections of

wireless receivers and transmitters.

The ADF41513 is designed on a high performance silicon

geranium (SiGe), bipolar complementary metal-oxide

semiconductor (BiCMOS) process, achieving a normalized

phase noise floor of −235 dBc/Hz. The phase frequency

detector (PFD) operates up to 250 MHz (integer N mode)/

125 MHz (fractional-N mode) for improved phase noise and

spur performance. The variable modulus, ∑-Δ modulator allows

extremely fine resolution when using a 49-bit divide value. The

ADF41513 can be used as an integer N phase-locked loop

(PLL), or it can be used as a fractional-N PLL with either a fixed

modulus for subhertz frequency resolution or variable modulus

for subhertz exact frequency resolution.

A complete PLL is implemented when the synthesizer is used

with an external loop filter and voltage controlled oscillator

(VCO). The 26.5 GHz bandwidth eliminates the need for a

frequency doubler or divider stage, simplifying system

architecture and reducing cost. The ADF41513 is packaged in a

compact, 24-lead, 4 mm × 4 mm LFCSP.

FUNCTIONAL BLOCK DIAGRAM

LOCK

DETECT

DATA

32-BIT

DATA

CLK

GND

DIV

OUT

DD1

DD2

DD3

DD4

DD5

REG1

GND

REG2

OUTPUT

MUX

MUXOUT

–

HIGH-Z

PHASE

FREQUENCY

DETECTOR

ADF41513

25-BIT FIXED/49-BIT VARIABLE

FRACTIONAL INTERPOLATOR

FRACTION

VALUE

INTEGER

VALUE

CHARGE

PUMP

1.8V

REGULATOR

DATA

REFERENCE

SET

REF

×2

DOUBLER

5-BIT

R COUNTER

÷2

DIVIDER

MODULUS

VALUE

N COUNTER

–

DLD

DC1

DC2

16805-001

Figure 1.

ADF41513 Data Sheet

Rev. 0 | Page 2 of 30

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications ....................................................................................... 1

General Description ......................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 2

Specifications ..................................................................................... 3

Timing Characteristics ................................................................ 5

Absolute Maximum Ratings ............................................................ 6

Thermal Resistance ...................................................................... 6

ESD Caution .................................................................................. 6

Pin Configuration and Function Description .............................. 7

Typical Performance Characteristics ............................................. 9

Theory of Operation ...................................................................... 11

Reference Input ........................................................................... 11

RF Input Stage ............................................................................. 11

N Divider and R Counter .......................................................... 11

R Counter .................................................................................... 12

PFD and Charge Pump .............................................................. 12

MUXOUT .................................................................................... 12

Lock Detector .............................................................................. 12

Readback ...................................................................................... 13

Input Shift Registers ................................................................... 13

Program Modes .......................................................................... 13

Applications information .............................................................. 28

Initialization Sequence .............................................................. 28

RF Synthesizer: A Worked Example of 25-Bit Fixed Modulus

Mode ............................................................................................ 28

RF Synthesizer: A Worked Example of Variable Modulus

Mode ............................................................................................ 28

Modulus ....................................................................................... 28

Reference Doubler and Reference Divider ............................. 28

Spur Mechanisms ....................................................................... 29

Phase Resync ............................................................................... 29

Outline Dimensions ....................................................................... 30

Ordering Guide .......................................................................... 30

REVISION HISTORY

1/2019—Revision 0: Initial Version

Data Sheet ADF41513

Rev. 0 | Page 3 of 30

SPECIFICATIONS

DDx

= AV

DD1

= AV

DD2

= AV

DD3

= AV

DD4

= AV

DD5

= V

= 3.3 V ± 5%, GND = 0 V, R

SET

= 1.8 kΩ, dBm referred to 50 Ω, T

= T

MIN

(−40°C)

to T

MAX

(+105°C), unless otherwise noted.

Table 1.

Parameter Min Typ Max Unit Test Conditions/Comments

RADIO FREQUENCY (RF)

CHARACTERISTICS

8/9 Prescaler

RF Input Frequency (f

RFIN

) Range 1 26.5 GHz Recommended input power of −5 dBm to

+5 dBm, operation at this frequency range is

limited to 70°C to T

MIN

1 24 GHz Operation at this frequency range is T

MAX

to T

MIN

RF Input Sensitivity −11 dBm Refer to Figure 10 and Figure 11 for more

information

4/5 Prescaler

RFIN

Range 1 16 GHz For lower frequencies, ensure slew rate >

320 V/µs

RF Input Sensitivity Range −7 +5 dBm Measured single-ended to RF

A via a 1 pF series

capacitor, 1 pF capacitor to GND on RF

INPUT REFERENCE FREQUENCY

(REF

) CHARACTERISTICS

REF

Input

Frequency 10 800 MHz

Voltage Range 0 1.8 V

Sensitivity Range

−10

dBm

Biased at 1 V (ac coupling ensures 1 V bias), use

square wave at low power and/or frequency to

ensure slew rate is > 320 V/µs; for best inband

phase noise performance, ensure slew rate >

500 V/µs

Capacitance 10 pF

Current

±150

µA

Doubler Input Frequency 225 MHz Maximum reference frequency when the

doubler is enabled

MAXIMUM PFD FREQUENCY

Integer N Mode 250 MHz

Fractional-N Mode 125 MHz

N DIVIDER RANGE

16-Bit N Divider Range

Integer N Mode 20 511 4/5 prescaler

64 1023 8/9 prescaler

Fractional-N Mode 23 511 4/5 prescaler

1023

8/9 prescaler

CHARGE PUMP (CP)

CP Current (I

) Sink and Source Programmable

High Value 7.2 mA With R

SET

= 1.8 kΩ

Low Value 0.45 mA

Absolute Accuracy 5 % With R

SET

= 1.8 kΩ

SET

Range 1.8 2.7 10 kΩ 5% accuracy

Three-State Leakage 2 nA V

= 0.9 V, T

= 25°C

Sink and Source Current Matching 5 % 0.7 V ≤ CP voltage (V

) ≤ V

− 0.7 V

vs. V

5 % 0.7 V ≤ V

≤ V

− 0.7 V

vs. Temperature 5 % V

= V

ADF41513 Data Sheet

Rev. 0 | Page 4 of 30

Parameter Min Typ Max Unit Test Conditions/Comments

LOGIC INPUTS

Input Voltage

High (V

) 1.4 V The serial port interface (SPI) block can accept

both 1.8 V or 3.3 V logic inputs

Low (V

) 0.6 V

Input Current (I

INH

, I

INL

) ±1 µA

Input Capacitance (C

) 10 pF

LOGIC OUTPUTS

Output Voltage

High (V

) 1.4 V MUXOUT voltage = 1.8 V, DLD voltage = 1.8 V

2.6 V MUXOUT voltage = 3.3 V, DLD voltage = 3.3 V

Low (V

) 0.4 V

Output High Current, Output Low

Current (I

, I

)

500 µA

POWER SUPPLIES

DD1

, AV

DD2

, AV

DD3

, AV

DD4

, AV

DD5

, V

3.135 3.3 3.465 V

DD1

2 3.2 mA Current drawn by AV

DD1

DD2

63.5 88 mA Current drawn by AV

DD2

DD3

2.1 3.6 mA Current drawn by AV

DD3

DD4

1.45 2 mA Current drawn by AV

DD4

DD5

Current drawn by AV

DD5

6 7 mA Current drawn by V

TOTAL

95.1 128.8 mA Total current drawn by AV

DDx

and V

Power-Down Mode 100 µA T

= 25°C, CE is low, total of all rails

NOISE CHARACTERISTICS

Normalized Phase Noise Floor

(PN

SYNTH

)

In Integer N Mode

−235 dBc/Hz PLL loop bandwidth (BW) = 1 MHz (Integer N

mode)

In Fractional-N Mode

−231 dBc/Hz PLL loop BW = 1 MHz (fractional-N mode)

Normalized 1∕f Noise (PN

1_f

)

−128 dBc/Hz 10 kHz offset, normalized to 1 GHz

SPURIOUS SIGNALS

Reference Spurious

−90

dBc

At reference = 100 MHz, PLL loop BW = 40 kHz

PFD Spurious −87 dBc At PFD = 50 MHz, PLL loop BW = 40 kHz

In-Band Integer Boundary

Spurious

−45 dBc 10 kHz offset, PLL loop BW = 250 kHz

= 25°C, AV

DDx

= 3.3 V (where x = 1, 2, 3, or 4), prescaler (P) = 8/9, f

RFIN

= 26.5 GHz, REF

= 124 MHz, PFD frequency input (f

PFD

) = 124 MHz.

The synthesizer phase noise floor is estimated by measuring the inband phase noise at the output of the VCO and subtracting 20 log N (where N is the N divider value)

and 10 log f

PFD

. PN

SYNTH

is the total phase noise measured at the VCO output (PN

TOT

) − 10 log f

PFD

− 20 log N.

The PLL phase noise is composed of 1/f (flicker) noise plus the normalized PLL noise floor. The formula for calculating the 1/f noise contribution at an RF frequency, f

RF,

and at a frequency offset, f, is given by phase noise (PN) = P

1_f

+ 10 log(10 kHz/f) + 20 log(f

/1 GHz). Both the normalized phase noise floor and flicker noise are

modeled in the ADIsimPLL.