mips单周期.zip （331个子文件） 
_info 5KB _vmake 26B project_1.vpr.ammdb 246B project_1.root_partition.cmp.ammdb 207B project_1.map.ammdb 137B p1-test .asm 824B project_1.vt.bak 3KB project_1_run_msim_rtl_verilog.do.bak 1KB NPC.v.bak 1KB alu.v.bak 877B controller.v.bak 410B dm_1k.v.bak 316B select_wr.v.bak 315B select_in_B.v.bak 290B GPR.v.bak 278B EXIT.v.bak 198B IFU.v.bak 165B im_1k.v.bak 162B select_pc.v.bak 153B PC.v.bak 128B project_1.v.bak 52B mips.v.bak 35B project_1_run_msim_rtl_verilog.do.bak1 1KB project_1_run_msim_rtl_verilog.do.bak10 1KB project_1_run_msim_rtl_verilog.do.bak11 2KB project_1_run_msim_rtl_verilog.do.bak2 1KB project_1_run_msim_rtl_verilog.do.bak3 1KB project_1_run_msim_rtl_verilog.do.bak4 1KB project_1_run_msim_rtl_verilog.do.bak5 1KB project_1_run_msim_rtl_verilog.do.bak6 1KB project_1_run_msim_rtl_verilog.do.bak7 1KB project_1_run_msim_rtl_verilog.do.bak8 1KB project_1_run_msim_rtl_verilog.do.bak9 1KB project_1.cmp.bpm 502B project_1.map.bpm 472B project_1.(3).cnf.cdb 736KB project_1.rtlv_sg.cdb 646KB project_1.(9).cnf.cdb 8KB project_1.(0).cnf.cdb 7KB project_1.(4).cnf.cdb 6KB project_1.(1).cnf.cdb 6KB project_1.rtlv_sg_swap.cdb 5KB project_1.(5).cnf.cdb 3KB project_1.(7).cnf.cdb 3KB project_1.cmp.cdb 3KB project_1.(8).cnf.cdb 2KB project_1.(6).cnf.cdb 2KB project_1.(10).cnf.cdb 2KB project_1.root_partition.cmp.cdb 2KB project_1.map.cdb 2KB project_1.sgdiff.cdb 2KB project_1.map_bb.cdb 2KB project_1.root_partition.map.cdb 2KB project_1.root_partition.map.hbdb.cdb 1KB project_1.(2).cnf.cdb 879B project_1.root_partition.map.reg_db.cdb 214B _primary.dat 4KB _primary.dat 2KB _primary.dat 1KB _primary.dat 1023B _primary.dat 997B logic_util_heursitic.dat 660B _primary.dat 542B _primary.dat 540B _primary.dat 438B _primary.dat 365B _primary.dat 303B _primary.dat 270B project_1.db_info 154B project_1.db_info 154B _primary.dbs 5KB _primary.dbs 2KB _primary.dbs 1KB _primary.dbs 1KB _primary.dbs 932B _primary.dbs 897B _primary.dbs 685B _primary.dbs 680B _primary.dbs 587B _primary.dbs 501B _primary.dbs 388B project_1.tiscmp.slow_1200mv_0c.ddb 95KB project_1.tiscmp.slow_1200mv_85c.ddb 95KB project_1.tiscmp.fast_1200mv_0c.ddb 94KB project_1.tiscmp.fastest_slow_1200mv_0c.ddb 94KB project_1.tiscmp.fastest_slow_1200mv_85c.ddb 94KB project_1.asm_labs.ddb 39KB project_1.tis_db_list.ddb 249B project_1.pti_db_list.ddb 191B project_1.root_partition.cmp.dfp 33B project_1_run_msim_rtl_verilog.do 2KB
Project1 VerilogHDL完成单周期处理器开发.docx 396KB mips指令.docx 20KB project_1.done 26B project_1.root_partition.map.dpi 1KB project_1.root_partition.map.hbdb.hb_info 46B project_1.pre_map.hdb 71KB project_1.rtlv.hdb 71KB project_1.(3).cnf.hdb 58KB project_1.sgdiff.hdb 12KB共 331 条
- 1
- 2
- 3
- 4
资源评论
