################################################################################
# Vivado (TM) v2019.2 (64-bit)
#
# README.txt: Please read the sections below to understand the steps required
# to simulate the design for a simulator, the directory structure
# and the generated exported files.
#
################################################################################
1. Simulate Design
To simulate design, cd to the simulator directory and execute the script.
For example:-
% cd questa
% ./top.sh
The export simulation flow requires the Xilinx pre-compiled simulation library
components for the target simulator. These components are referred using the
'-lib_map_path' switch. If this switch is specified, then the export simulation
will automatically set this library path in the generated script and update,
copy the simulator setup file(s) in the exported directory.
If '-lib_map_path' is not specified, then the pre-compiled simulation library
information will not be included in the exported scripts and that may cause
simulation errors when running this script. Alternatively, you can provide the
library information using this switch while executing the generated script.
For example:-
% ./top.sh -lib_map_path /design/questa/clibs
Please refer to the generated script header 'Prerequisite' section for more details.
2. Directory Structure
By default, if the -directory switch is not specified, export_simulation will
create the following directory structure:-
<current_working_directory>/export_sim/<simulator>
For example, if the current working directory is /tmp/test, export_simulation
will create the following directory path:-
/tmp/test/export_sim/questa
If -directory switch is specified, export_simulation will create a simulator
sub-directory under the specified directory path.
For example, 'export_simulation -directory /tmp/test/my_test_area/func_sim'
command will create the following directory:-
/tmp/test/my_test_area/func_sim/questa
By default, if -simulator is not specified, export_simulation will create a
simulator sub-directory for each simulator and export the files for each simulator
in this sub-directory respectively.
IMPORTANT: Please note that the simulation library path must be specified manually
in the generated script for the respective simulator. Please refer to the generated
script header 'Prerequisite' section for more details.
3. Exported script and files
Export simulation will create the driver shell script, setup files and copy the
design sources in the output directory path.
By default, when the -script_name switch is not specified, export_simulation will
create the following script name:-
<simulation_top>.sh (Unix)
When exporting the files for an IP using the -of_objects switch, export_simulation
will create the following script name:-
<ip-name>.sh (Unix)
Export simulation will create the setup files for the target simulator specified
with the -simulator switch.
For example, if the target simulator is "ies", export_simulation will create the
'cds.lib', 'hdl.var' and design library diectories and mappings in the 'cds.lib'
file.
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FPGA学习之-串口+ram ip核存储数据 (349个子文件)
__synthesis_is_complete__ 0B
__synthesis_is_complete__ 0B
xsim.ini.bak 26KB
elaborate.bat 1KB
simulate.bat 930B
compile.bat 840B
runme.bat 229B
runme.bat 229B
runme.bat 229B
uart_ram_t_r.bit 2.09MB
xsim_1.c 13KB
xsim_1.c 5KB
xsim_1.c 4KB
xsim.dbg 89KB
xsim.dbg 6KB
xsim.dbg 4KB
uart_ram_t_r_routed.dcp 267KB
uart_ram_t_r_physopt.dcp 246KB
uart_ram_t_r_placed.dcp 244KB
uart_ram_t_r_opt.dcp 190KB
uart_ram_t_r.dcp 51KB
uart_ram.dcp 30KB
uart_ram.dcp 30KB
uart_ram.dcp 30KB
uart_ram.dcp 24KB
uart_ram.dcp 24KB
compile.do 779B
compile.do 745B
compile.do 695B
compile.do 681B
simulate.do 331B
simulate.do 325B
simulate.do 325B
elaborate.do 203B
simulate.do 193B
wave.do 32B
wave.do 32B
wave.do 32B
wave.do 32B
simulate.do 11B
xsimk.exe 186KB
xsimk.exe 73KB
xsimk.exe 63KB
run.f 522B
run.f 502B
usage_statistics_webtalk.html 30KB
usage_statistics_ext_xsim.html 4KB
usage_statistics_ext_xsim.html 3KB
usage_statistics_ext_xsim.html 3KB
.xsim_webtallk.info 65B
.xsim_webtallk.info 64B
.xsim_webtallk.info 55B
xsim.ini 26KB
xsim.ini 26KB
xsimSettings.ini 1KB
xsimSettings.ini 1KB
webtalk_17020.backup.jou 1006B
webtalk.jou 1002B
webtalk_23580.backup.jou 1002B
webtalk_13936.backup.jou 996B
webtalk_5604.backup.jou 995B
vivado.jou 808B
vivado.jou 801B
vivado_6840.backup.jou 801B
vivado.jou 797B
ISEWrap.js 8KB
ISEWrap.js 8KB
ISEWrap.js 8KB
rundef.js 1KB
rundef.js 1KB
rundef.js 1KB
runme.log 69KB
runme.log 33KB
runme.log 25KB
webtalk_17020.backup.log 1KB
webtalk.log 1KB
webtalk_23580.backup.log 1KB
webtalk_13936.backup.log 1KB
webtalk_5604.backup.log 1KB
summary.log 980B
summary.log 980B
summary.log 980B
summary.log 980B
summary.log 980B
summary.log 980B
summary.log 980B
summary.log 980B
summary.log 980B
summary.log 980B
elaborate.log 638B
simulate.log 434B
xsimkernel.log 336B
xsimkernel.log 322B
xvlog.log 0B
xsimcrash.log 0B
xsimcrash.log 0B
uart_ram.lpr 343B
xsim.mem 18KB
xsim.mem 3KB
xsim.mem 3KB
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