2.源码
顶层模块：
`timescale 1ns / 1ps
module temp_top (
input clk, input rst_p,
output [7:0] weixuan,
output [7:0] duanxuan,
output temp_SCL,
inout temp_SDA
);
wire [7:0] read_data;
wire [7:0] read_data1;
wire [12:0] temp_sensor_data;
wire [3:0]int_data_ten;
wire [3:0]int_data_one;
wire [3:0] point_data_tho;
wire clk_out;
assign temp_sensor_data = { read_data,read_data1[7:3] };
div_count i_div_count (
.clk(clk),
.rst_n(~rst_p),
.clk_out(clk_out)
);
temp_sensor tempsensor (
.clk_out(clk_out),
.rst_n(~stop),
.scl(temp_SCL),
.sda(temp_SDA),
.read_data(read_data),
.read_data1(read_data1)
);
code_decode i_code_decode (
. clk(clk),
. temp_sensor_data(temp_sensor_data),
. int_data_ten(int_data_ten),
