/**
******************************************************************************
* @file stm32f4xx_rcc.c
* @author MCD Application Team
* @version V1.8.0
* @date 04-November-2016
* @brief This file provides firmware functions to manage the following
* functionalities of the Reset and clock control (RCC) peripheral:
* + Internal/external clocks, PLL, CSS and MCO configuration
* + System, AHB and APB busses clocks configuration
* + Peripheral clocks configuration
* + Interrupts and flags management
*
@verbatim
===============================================================================
##### RCC specific features #####
===============================================================================
[..]
After reset the device is running from Internal High Speed oscillator
(HSI 16MHz) with Flash 0 wait state, Flash prefetch buffer, D-Cache
and I-Cache are disabled, and all peripherals are off except internal
SRAM, Flash and JTAG.
(+) There is no prescaler on High speed (AHB) and Low speed (APB) busses;
all peripherals mapped on these busses are running at HSI speed.
(+) The clock for all peripherals is switched off, except the SRAM and FLASH.
(+) All GPIOs are in input floating state, except the JTAG pins which
are assigned to be used for debug purpose.
[..]
Once the device started from reset, the user application has to:
(+) Configure the clock source to be used to drive the System clock
(if the application needs higher frequency/performance)
(+) Configure the System clock frequency and Flash settings
(+) Configure the AHB and APB busses prescalers
(+) Enable the clock for the peripheral(s) to be used
(+) Configure the clock source(s) for peripherals which clocks are not
derived from the System clock (I2S, RTC, ADC, USB OTG FS/SDIO/RNG)
@endverbatim
******************************************************************************
* @attention
*
* <h2><center>© COPYRIGHT 2016 STMicroelectronics</center></h2>
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
* You may obtain a copy of the License at:
*
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32f4xx_rcc.h"
/** @addtogroup STM32F4xx_StdPeriph_Driver
* @{
*/
/** @defgroup RCC
* @brief RCC driver modules
* @{
*/
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* ------------ RCC registers bit address in the alias region ----------- */
#define RCC_OFFSET (RCC_BASE - PERIPH_BASE)
/* --- CR Register ---*/
/* Alias word address of HSION bit */
#define CR_OFFSET (RCC_OFFSET + 0x00)
#define HSION_BitNumber 0x00
#define CR_HSION_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (HSION_BitNumber * 4))
/* Alias word address of CSSON bit */
#define CSSON_BitNumber 0x13
#define CR_CSSON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (CSSON_BitNumber * 4))
/* Alias word address of PLLON bit */
#define PLLON_BitNumber 0x18
#define CR_PLLON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLLON_BitNumber * 4))
/* Alias word address of PLLI2SON bit */
#define PLLI2SON_BitNumber 0x1A
#define CR_PLLI2SON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLLI2SON_BitNumber * 4))
/* Alias word address of PLLSAION bit */
#define PLLSAION_BitNumber 0x1C
#define CR_PLLSAION_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLLSAION_BitNumber * 4))
/* --- CFGR Register ---*/
/* Alias word address of I2SSRC bit */
#define CFGR_OFFSET (RCC_OFFSET + 0x08)
#define I2SSRC_BitNumber 0x17
#define CFGR_I2SSRC_BB (PERIPH_BB_BASE + (CFGR_OFFSET * 32) + (I2SSRC_BitNumber * 4))
/* --- BDCR Register ---*/
/* Alias word address of RTCEN bit */
#define BDCR_OFFSET (RCC_OFFSET + 0x70)
#define RTCEN_BitNumber 0x0F
#define BDCR_RTCEN_BB (PERIPH_BB_BASE + (BDCR_OFFSET * 32) + (RTCEN_BitNumber * 4))
/* Alias word address of BDRST bit */
#define BDRST_BitNumber 0x10
#define BDCR_BDRST_BB (PERIPH_BB_BASE + (BDCR_OFFSET * 32) + (BDRST_BitNumber * 4))
/* --- CSR Register ---*/
/* Alias word address of LSION bit */
#define CSR_OFFSET (RCC_OFFSET + 0x74)
#define LSION_BitNumber 0x00
#define CSR_LSION_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (LSION_BitNumber * 4))
/* --- DCKCFGR Register ---*/
/* Alias word address of TIMPRE bit */
#define DCKCFGR_OFFSET (RCC_OFFSET + 0x8C)
#define TIMPRE_BitNumber 0x18
#define DCKCFGR_TIMPRE_BB (PERIPH_BB_BASE + (DCKCFGR_OFFSET * 32) + (TIMPRE_BitNumber * 4))
/* --- CFGR Register ---*/
#define RCC_CFGR_OFFSET (RCC_OFFSET + 0x08)
#if defined(STM32F410xx)
/* Alias word address of MCO1EN bit */
#define RCC_MCO1EN_BIT_NUMBER 0x8
#define RCC_CFGR_MCO1EN_BB (PERIPH_BB_BASE + (RCC_CFGR_OFFSET * 32) + (RCC_MCO1EN_BIT_NUMBER * 4))
/* Alias word address of MCO2EN bit */
#define RCC_MCO2EN_BIT_NUMBER 0x9
#define RCC_CFGR_MCO2EN_BB (PERIPH_BB_BASE + (RCC_CFGR_OFFSET * 32) + (RCC_MCO2EN_BIT_NUMBER * 4))
#endif /* STM32F410xx */
/* ---------------------- RCC registers bit mask ------------------------ */
/* CFGR register bit mask */
#define CFGR_MCO2_RESET_MASK ((uint32_t)0x07FFFFFF)
#define CFGR_MCO1_RESET_MASK ((uint32_t)0xF89FFFFF)
/* RCC Flag Mask */
#define FLAG_MASK ((uint8_t)0x1F)
/* CR register byte 3 (Bits[23:16]) base address */
#define CR_BYTE3_ADDRESS ((uint32_t)0x40023802)
/* CIR register byte 2 (Bits[15:8]) base address */
#define CIR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + 0x0C + 0x01))
/* CIR register byte 3 (Bits[23:16]) base address */
#define CIR_BYTE3_ADDRESS ((uint32_t)(RCC_BASE + 0x0C + 0x02))
/* BDCR register base address */
#define BDCR_ADDRESS (PERIPH_BASE + BDCR_OFFSET)
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
static __I uint8_t APBAHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9};
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/** @defgroup RCC_Private_Functions
* @{
*/
/** @defgroup RCC_Group1 Internal and external clocks, PLL, CSS and MCO configuration functions
* @brief Internal and external clocks, PLL, CSS and MCO configuration functions
*
@verbatim
===================================================================================
##### Internal and external clocks, PLL, CSS and MCO configuration functions #####
===================================================================================
[..]
This section provide functions allowing to configure the internal/exter
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STM32F407系统时钟配置和定时器中断配置 (IAR工程文件)
共187个文件
h:60个
c:51个
xcl:20个
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1.配置系统时钟为168MHz,AHB总线168MHz,APB1总线42MHz,APB2总线84MHz; 2.配置一个TIM进行计时,让一颗LED以点亮500ms,熄灭500ms的方式闪烁; 1.系统的时钟由PLL提供; 2.PLL的时钟来源为HSE(外部高速时钟); 3.系统的最高时钟为168MHz; 4.在此文件中定义的HSE频率为25MHz; #define PLL_M 8 #define PLL_N 336 #define PLL_P 2 #define PLL_Q 7 ErrorStatus SystemClockConfig(void) { ErrorStatus HSEStartUpStatus; RCC_DeInit(); /* 使能外部晶振时钟 */ RCC_HSEConfig(RCC_HSE_ON); /* 等待外部晶振源启振 */ HSEStartUpStatus = RCC_WaitForHSEStartUp(); while(HSEStar
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STM32F407系统时钟配置和定时器中断配置 (IAR工程文件) (187个子文件)
STM32F407Project_Test.Debug.cspy.bat 2KB
STM32F407Project_Test.pbd.browse 1.76MB
stm32f4xx_rcc.c 134KB
stm32f4xx_tim.c 122KB
stm32f4xx_rtc.c 101KB
stm32f4xx_dfsdm.c 85KB
stm32f4xx_adc.c 67KB
stm32f4xx_can.c 65KB
stm32f4xx_flash.c 62KB
stm32f4xx_fmc.c 61KB
stm32f4xx_dsi.c 61KB
system_stm32f4xx.c 60KB
stm32f4xx_cryp_aes.c 57KB
stm32f4xx_fmpi2c.c 57KB
stm32f4xx_usart.c 57KB
stm32f4xx_i2c.c 53KB
stm32f4xx_dma.c 52KB
stm32f4xx_spi.c 52KB
stm32f4xx_sai.c 48KB
stm32f4xx_fsmc.c 45KB
stm32f4xx_pwr.c 42KB
stm32f4xx_ltdc.c 39KB
stm32f4xx_sdio.c 38KB
stm32f4xx_cryp.c 35KB
stm32f4xx_lptim.c 34KB
stm32f4xx_qspi.c 32KB
stm32f4xx_dma2d.c 27KB
stm32f4xx_dac.c 26KB
stm32f4xx_hash.c 26KB
stm32f4xx_gpio.c 25KB
stm32f4xx_cec.c 24KB
stm32f4xx_dcmi.c 18KB
stm32f4xx_spdifrx.c 17KB
stm32f4xx_syscfg.c 17KB
stm32f4xx_rng.c 14KB
misc.c 11KB
stm32f4xx_cryp_tdes.c 11KB
stm32f4xx_wwdg.c 10KB
stm32f4xx_cryp_des.c 10KB
stm32f4xx_exti.c 10KB
stm32f4xx_hash_sha1.c 10KB
stm32f4xx_hash_md5.c 9KB
stm32f4xx_iwdg.c 9KB
stm32f4xx_dbgmcu.c 7KB
stm32f4xx_flash_ramfunc.c 5KB
stm32f4xx_it.c 4KB
stm32f4xx_crc.c 4KB
usart.c 3KB
delay.c 2KB
timer.c 1KB
led.c 1KB
sysclk.c 1KB
main.c 358B
STM32F407Project_Test.crun 384B
STM32F407Project_Test.dbgdt 57KB
STM32F407Project_Test.dep 28KB
STM32F407Project_Test.dnx 3KB
STM32F407Project_Test.ewd 105KB
STM32F407Project_Test.ewp 75KB
STM32F407Project_Test.ewt 173KB
STM32F407Project.eww 179B
stm32f4xx.h 918KB
arm_math.h 246KB
core_cm7.h 135KB
core_cm4.h 112KB
core_cm3.h 101KB
core_sc300.h 100KB
stm32f4xx_tim.h 50KB
stm32f4xx_rcc.h 50KB
stm32f4xx_dfsdm.h 45KB
stm32f4xx_fmc.h 44KB
core_sc000.h 43KB
core_cm0plus.h 43KB
stm32f4xx_dsi.h 40KB
stm32f4xx_rtc.h 40KB
core_cm0.h 35KB
stm32f4xx_adc.h 32KB
stm32f4xx_i2c.h 31KB
stm32f4xx_gpio.h 29KB
stm32f4xx_dma.h 28KB
stm32f4xx_sai.h 28KB
core_cmInstr.h 27KB
stm32f4xx_can.h 27KB
stm32f4xx_fsmc.h 27KB
stm32f4xx_flash.h 25KB
core_cmSimd.h 22KB
stm32f4xx_sdio.h 22KB
stm32f4xx_ltdc.h 21KB
stm32f4xx_spi.h 21KB
stm32f4xx_qspi.h 20KB
stm32f4xx_dma2d.h 19KB
stm32f4xx_fmpi2c.h 19KB
core_cmFunc.h 18KB
stm32f4xx_usart.h 18KB
stm32f4xx_lptim.h 17KB
stm32f4xx_dac.h 15KB
stm32f4xx_cryp.h 14KB
stm32f4xx_syscfg.h 14KB
stm32f4xx_dcmi.h 13KB
stm32f4xx_cec.h 12KB
共 187 条
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