Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Device Comparison......................................................... 8
6 Pin Configuration and Functions...................................8
6.1 Unused Pins .............................................................14
7 Specifications................................................................ 15
7.1 Absolute Maximum Ratings...................................... 15
7.2 ESD Ratings............................................................. 15
7.3 Recommended Operating Conditions.......................15
7.4 Thermal Information..................................................16
7.5 Electrical Characteristics...........................................16
7.6 Power-Up Timing...................................................... 18
7.7 Reset Timing.............................................................19
7.8 MII Serial Management Timing................................. 19
7.9 RGMII Timing............................................................19
7.10 GMII Transmit Timing
(2)
......................................... 20
7.11 GMII Receive Timing
(2)
.......................................... 20
7.12 100-Mbps MII Transmit Timing
(1)
........................... 20
7.13 100-Mbps MII Receive Timing
(2)
............................ 20
7.14 10-Mbps MII Transmit Timing
(2)
............................. 21
7.15 10-Mbps MII Receive Timing
(2)
.............................. 21
7.16 DP83867IR/CR Start of Frame Detection Timing... 21
7.17 Timing Diagrams ....................................................25
7.18 Typical Characteristics............................................ 30
8 Detailed Description......................................................31
8.1 Overview................................................................... 31
8.2 Functional Block Diagram......................................... 32
8.3 Feature Description...................................................34
8.4 Device Functional Modes..........................................37
8.5 Programming............................................................ 51
8.6 Register Maps...........................................................59
9 Application and Implementation................................ 118
9.1 Application Information............................................118
9.2 Typical Application.................................................. 118
10 Power Supply Recommendations............................125
11 Layout......................................................................... 128
11.1 Layout Guidelines................................................. 128
11.2 Layout Example.................................................... 130
12 Device and Documentation Support........................131
12.1 Documentation Support........................................ 131
12.2 Related Links........................................................ 131
12.3 Receiving Notification of Documentation Updates131
12.4 Support Resources............................................... 131
12.5 Electrostatic Discharge Caution............................131
12.6 Glossary................................................................131
12.7 Trademarks...........................................................131
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision F (October 2019) to Revision G (August 2022) Page
• Updated Start of Frame Detect for IEEE 1588 time stamp.................................................................................1
• Added following wording to the end of first paragraph in Section 8.4.3.9 "DP83867 devices manufactured
after August, 2022, have an increased random seed value that now includes 255 different seed values to
expedite Auto-MDIX resolution with a link partner."..........................................................................................46
• Removed Reg 0x01D5 Programmable Gain Register (PROG_GAIN)............................................................. 59
• Changed Bit 11:10 SPEED_OPT_ATTEMPT_CNT to RW description in ........................................................79
• Changed bits 15:9, so that bit 12 can be '1'. Bit 7 description updated Section 8.6.31 ................................... 90
• Added Register 0x008A....................................................................................................................................96
• Added Register 0x00B3....................................................................................................................................97
• Added Register 0x00C0....................................................................................................................................97
• Added Register 0x0100.................................................................................................................................... 98
Changes from Revision E (March 2017) to Revision F (October 2019) Page
• Added "Time Sensitive Network (TSN) Compliant" to Section 1 ....................................................................... 1
• Changed "Fast Link up / Link Drop Modes" to "Fast Link Drop Mode" in Section 1 .......................................... 1
• Added "Field Bus Support" to Section 2 ............................................................................................................ 1
• Changed 'TX_EN / TX_CTRL' pin type in Pin Functions.................................................................................. 10
• Deleted "NOTE: Internal Pull-Up/Pull-Down resistors on the IO pins are disabled when the device enters
functional mode after power up." from Pin Functions....................................................................................... 10
• Added XI pin voltage ratings to Section 7.1 .....................................................................................................15
• Added XI Input Voltage section to Section 7.5 .................................................................................................16
• Changed links to RGMII timing diagrams in Section 7.9 ................................................................................. 19
• Changed T
holdR
parameter description in Section 7.9 ..................................................................................... 19
• Added table note explaining how Duty Cycle % must be interpreted in Section 7.9 ....................................... 19
DP83867IR, DP83867CR
SNLS484G – FEBRUARY 2015 – REVISED OCTOBER 2022
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