没有合适的资源？快使用搜索试试~ 我知道了~
TMS320F28379寄存器手册.pdf
需积分: 47 47 下载量 91 浏览量
2019-12-11
00:02:09
上传
评论 3
收藏 15.54MB PDF 举报
温馨提示
试读
2597页
TMS320F28379寄存器手册 TMS320F2837xD 是一款功能强大的 32 位浮点微控制器单元 (MCU)，针对高级闭环控制 应用 而设计，例如工业驱动器和伺服电机控制、太阳能逆变器和转换器、数字电源、电力输送以及电力线通信。
资源推荐
资源详情
资源评论
TMS320F2837xD Dual-Core Delfino
Microcontrollers
Technical Reference Manual
Literature Number: SPRUHM8H
December 2013–Revised January 2019
2
SPRUHM8H–December 2013–Revised January 2019
Submit Documentation Feedback
Copyright © 2013–2019, Texas Instruments Incorporated
Contents
Contents
Preface....................................................................................................................................... 79
1 C2000Ware Quick Start Guide.............................................................................................. 80
1.1 Package Structure.......................................................................................................... 81
1.1.1 Documentation..................................................................................................... 81
1.1.2 Devices ............................................................................................................. 81
1.1.3 Libraries ............................................................................................................ 81
1.2 C2000Ware GUI............................................................................................................ 81
1.3 Updating C2000Ware...................................................................................................... 82
1.4 Code Composer Studio.................................................................................................... 82
2 C28x Processor.................................................................................................................. 83
2.1 Overview..................................................................................................................... 84
2.2 Floating-Point Unit ......................................................................................................... 84
2.3 Trigonometric Math Unit .................................................................................................. 84
2.4 Viterbi, Complex Math, and CRC Unit II (VCU-II) ..................................................................... 85
3 System Control .................................................................................................................. 86
3.1 Introduction.................................................................................................................. 87
3.2 System Control Functional Description.................................................................................. 87
3.2.1 Device Identification .............................................................................................. 87
3.2.2 Device Configuration Registers ................................................................................. 88
3.3 Resets ....................................................................................................................... 88
3.3.1 Reset Sources ..................................................................................................... 88
3.3.2 External Reset (XRS)............................................................................................. 89
3.3.3 Power-On Reset (POR) .......................................................................................... 89
3.3.4 Debugger Reset (SYSRS) ....................................................................................... 89
3.3.5 Watchdog Reset (WDRS) ........................................................................................ 90
3.3.6 NMI Watchdog Reset (NMIWDRS) ............................................................................. 90
3.3.7 DCSM Safe Code Copy Reset (SCCRESET) ................................................................. 90
3.3.8 Hibernate Reset (HIBRESET) ................................................................................... 90
3.3.9 Hardware BIST Reset (HWBISTRS)............................................................................ 90
3.3.10 Test Reset (TRST) ............................................................................................... 90
3.4 Peripheral Interrupts ....................................................................................................... 90
3.4.1 Interrupt Concepts................................................................................................. 91
3.4.2 Interrupt Architecture.............................................................................................. 91
3.4.3 Interrupt Entry Sequence......................................................................................... 93
3.4.4 Configuring and Using Interrupts................................................................................ 94
3.4.5 PIE Channel Mapping ............................................................................................ 96
3.4.6 Vector Tables ...................................................................................................... 97
3.5 Exceptions and Non-Maskable Interrupts ............................................................................. 103
3.5.1 Configuring and Using NMIs ................................................................................... 103
3.5.2 Emulation Considerations ...................................................................................... 103
3.5.3 NMI Sources...................................................................................................... 104
3.5.4 Illegal Instruction Trap (ITRAP) ................................................................................ 104
3.6 Safety Features ........................................................................................................... 104
3.6.1 Write Protection on Registers .................................................................................. 104
3.6.2 Missing Clock Detection Logic ................................................................................. 105
www.ti.com
3
SPRUHM8H–December 2013–Revised January 2019
Submit Documentation Feedback
Copyright © 2013–2019, Texas Instruments Incorporated
Contents
3.6.3 PLLSLIP Detection .............................................................................................. 106
3.6.4 CPU1 and CPU2 PIE Vector Address Validity Check ...................................................... 106
3.6.5 NMIWDs .......................................................................................................... 107
3.6.6 ECC and Parity Enabled RAMs, Shared RAMs Protection ................................................ 107
3.6.7 ECC Enabled Flash Memory................................................................................... 107
3.6.8 ERRORSTS Pin.................................................................................................. 107
3.7 Clocking ................................................................................................................... 108
3.7.1 Clock Sources.................................................................................................... 110
3.7.2 Derived Clocks ................................................................................................... 112
3.7.3 Device Clock Domains .......................................................................................... 112
3.7.4 XCLKOUT......................................................................................................... 113
3.7.5 Clock Connectivity ............................................................................................... 114
3.7.6 Clock Source and PLL Setup .................................................................................. 115
3.8 32-Bit CPU Timers 0/1/2................................................................................................. 118
3.9 Watchdog Timers ......................................................................................................... 120
3.9.1 Servicing the Watchdog Timer ................................................................................. 120
3.9.2 Minimum Window Check ....................................................................................... 121
3.9.3 Watchdog Reset or Watchdog Interrupt Mode............................................................... 121
3.9.4 Watchdog Operation in Low Power Modes .................................................................. 122
3.9.5 Emulation Considerations ...................................................................................... 122
3.10 Low Power Modes ........................................................................................................ 123
3.10.1 IDLE .............................................................................................................. 123
3.10.2 STANDBY ....................................................................................................... 123
3.10.3 HALT ............................................................................................................. 124
3.10.4 HIB................................................................................................................ 124
3.11 Memory Controller Module .............................................................................................. 126
3.11.1 Functional Description ......................................................................................... 126
3.12 Flash and OTP Memory ................................................................................................. 134
3.12.1 Features.......................................................................................................... 134
3.12.2 Flash Tools ...................................................................................................... 134
3.12.3 Default Flash Configuration ................................................................................... 135
3.12.4 Flash Bank, OTP and Pump .................................................................................. 135
3.12.5 Flash Module Controller (FMC) ............................................................................... 135
3.12.6 Flash and OTP Power-Down Modes and Wakeup......................................................... 136
3.12.7 Flash and OTP Performance.................................................................................. 138
3.12.8 Flash Read Interface ........................................................................................... 138
3.12.9 Erase/Program Flash........................................................................................... 140
3.12.10 Error Correction Code (ECC) Protection ................................................................... 141
3.12.11 Reserved Locations Within Flash and OTP ............................................................... 145
3.12.12 Procedure to Change the Flash Control Registers ....................................................... 145
3.12.13 Flash Pump Ownership Semaphore........................................................................ 145
3.13 Dual Code Security Module (DCSM)................................................................................... 147
3.13.1 Functional Description ......................................................................................... 147
3.13.2 CSM Impact on Other On-Chip Resources ................................................................. 153
3.13.3 Incorporating Code Security in User Applications.......................................................... 154
3.14 JTAG ....................................................................................................................... 158
3.15 F2837xD System Control Registers.................................................................................... 160
3.15.1 F2837xD System Control Base Addresses ................................................................. 160
3.15.2 CPUTIMER_REGS Registers................................................................................. 161
3.15.3 PIE_CTRL_REGS Registers .................................................................................. 168
3.15.4 WD_REGS Registers .......................................................................................... 220
3.15.5 NMI_INTRUPT_REGS Registers............................................................................. 226
3.15.6 XINT_REGS Registers......................................................................................... 240
www.ti.com
4
SPRUHM8H–December 2013–Revised January 2019
Submit Documentation Feedback
Copyright © 2013–2019, Texas Instruments Incorporated
Contents
3.15.7 DMA_CLA_SRC_SEL_REGS Registers .................................................................... 249
3.15.8 FLASH_PUMP_SEMAPHORE_REGS Registers .......................................................... 256
3.15.9 DEV_CFG_REGS Registers .................................................................................. 258
3.15.10 CLK_CFG_REGS Registers ................................................................................. 325
3.15.11 CPU_SYS_REGS Registers................................................................................. 348
3.15.12 ROM_PREFETCH_REGS Registers ....................................................................... 388
3.15.13 DCSM_Z1_OTP Registers................................................................................... 390
3.15.14 DCSM_Z2_OTP Registers................................................................................... 397
3.15.15 DCSM_Z1_REGS Registers................................................................................. 404
3.15.16 DCSM_Z2_REGS Registers................................................................................. 424
3.15.17 DCSM_COMMON_REGS Registers ....................................................................... 444
3.15.18 MEM_CFG_REGS Registers................................................................................ 451
3.15.19 ACCESS_PROTECTION_REGS Registers ............................................................... 496
3.15.20 MEMORY_ERROR_REGS Registers ...................................................................... 516
3.15.21 ROM_WAIT_STATE_REGS Registers..................................................................... 533
3.15.22 FLASH_CTRL_REGS Registers ............................................................................ 535
3.15.23 FLASH_ECC_REGS Registers ............................................................................. 544
3.15.24 CPU_ID_REGS Registers ................................................................................... 567
3.15.25 UID_REGS Registers......................................................................................... 569
4 ROM Code and Peripheral Booting ..................................................................................... 578
4.1 Introduction ................................................................................................................ 579
4.2 Device Boot Philosophy.................................................................................................. 579
4.3 Device Boot Modes....................................................................................................... 579
4.4 Configuring Boot Mode Pins ............................................................................................ 580
4.5 Configuring Get Boot Options........................................................................................... 581
4.6 Configuring Emulation Boot Options ................................................................................... 582
4.7 Device Boot Flow Diagrams............................................................................................. 584
4.7.1 Emulation Boot Flow Diagrams ................................................................................ 585
4.7.2 Standalone and Hibernate Boot Flow Diagrams............................................................. 587
4.8 Device Reset and Exception Handling................................................................................. 589
4.8.1 Reset Causes and Handling.................................................................................... 589
4.8.2 Exceptions and Interrupts Handling ........................................................................... 590
4.9 Boot ROM Description ................................................................................................... 590
4.9.1 Entry Points....................................................................................................... 590
4.9.2 Wait Points........................................................................................................ 591
4.9.3 Memory Maps .................................................................................................... 591
4.9.4 Boot Modes....................................................................................................... 594
4.9.5 Boot Data Stream Structure .................................................................................... 607
4.9.6 GPIO Assignments .............................................................................................. 609
4.9.7 Boot IPC .......................................................................................................... 611
4.9.8 Clock Initializations .............................................................................................. 614
4.9.9 Wait State Configuration........................................................................................ 615
4.9.10 Boot Status information ........................................................................................ 615
4.9.11 ROM Version .................................................................................................... 617
5 Direct Memory Access (DMA)............................................................................................. 619
5.1 Introduction ................................................................................................................ 620
5.2 Architecture................................................................................................................ 621
5.2.1 Block Diagram.................................................................................................... 621
5.2.2 Common Peripheral Architecture .............................................................................. 621
5.2.3 Peripheral Interrupt Event Trigger Sources .................................................................. 623
5.2.4 DMA Bus.......................................................................................................... 628
5.3 Address Pointer and Transfer Control ................................................................................. 628
5.4 Pipeline Timing and Throughput........................................................................................ 633
www.ti.com
5
SPRUHM8H–December 2013–Revised January 2019
Submit Documentation Feedback
Copyright © 2013–2019, Texas Instruments Incorporated
Contents
5.5 CPU and CLA Arbitration ................................................................................................ 634
5.6 Channel Priority ........................................................................................................... 635
5.6.1 Round-Robin Mode.............................................................................................. 635
5.6.2 Channel 1 High Priority Mode.................................................................................. 636
5.7 Overrun Detection Feature .............................................................................................. 636
5.8 DMA Registers ............................................................................................................ 637
5.8.1 DMA Base Addresses........................................................................................... 637
5.8.2 DMA_REGS Registers .......................................................................................... 638
5.8.3 DMA_CH_REGS Registers..................................................................................... 643
6 Control Law Accelerator (CLA)........................................................................................... 671
6.1 Control Law Accelerator (CLA) Overview ............................................................................. 672
6.2 CLA Interface.............................................................................................................. 674
6.2.1 CLA Memory ..................................................................................................... 674
6.2.2 CLA Memory Bus ................................................................................................ 675
6.2.3 Shared Peripherals and EALLOW Protection................................................................ 675
6.2.4 CLA Tasks and Interrupt Vectors.............................................................................. 676
6.2.5 CLA Software Interrupt to CPU ................................................................................ 678
6.3 CLA and CPU Arbitration ................................................................................................ 678
6.3.1 CLA Message RAM ............................................................................................. 678
6.4 CLA Configuration and Debug .......................................................................................... 680
6.4.1 Building a CLA Application ..................................................................................... 680
6.4.2 Typical CLA Initialization Sequence........................................................................... 680
6.4.3 Debugging CLA Code........................................................................................... 681
6.4.4 CLA Illegal Opcode Behavior .................................................................................. 682
6.4.5 Resetting the CLA ............................................................................................... 682
6.5 Pipeline..................................................................................................................... 684
6.5.1 Pipeline Overview................................................................................................ 684
6.5.2 CLA Pipeline Alignment......................................................................................... 684
6.5.3 Parallel Instructions.............................................................................................. 688
6.6 Instruction Set ............................................................................................................. 689
6.6.1 Instruction Descriptions ......................................................................................... 689
6.6.2 Addressing Modes and Encoding.............................................................................. 691
6.6.3 Instructions ....................................................................................................... 693
6.7 CLA Registers............................................................................................................. 804
6.7.1 CLA Base Addresses............................................................................................ 804
6.7.2 CLA_REGS Registers........................................................................................... 805
6.7.3 CLA_SOFTINT_REGS Registers.............................................................................. 846
7 Interprocessor Communication (IPC) .................................................................................. 850
7.1 Interprocessor Communication ......................................................................................... 851
7.2 Message RAMs ........................................................................................................... 852
7.3 IPC Flags and Interrupts................................................................................................. 852
7.4 IPC Command Registers ................................................................................................ 852
7.5 Free-Running Counter ................................................................................................... 852
7.6 IPC Communication Protocol............................................................................................ 853
7.7 IPC Registers.............................................................................................................. 854
7.7.1 IPC Base Addresses ............................................................................................ 854
7.7.2 IPC_REGS_CPU1 Registers................................................................................... 855
7.7.3 IPC_REGS_CPU2 Registers................................................................................... 888
8 General-Purpose Input/Output (GPIO) ................................................................................. 921
8.1 GPIO Overview ........................................................................................................... 922
8.2 Configuration Overview .................................................................................................. 923
8.3 Digital General-Purpose I/O Control.................................................................................... 923
8.4 Input Qualification......................................................................................................... 925
剩余2596页未读，继续阅读
资源评论
MiasanPartner
- 粉丝: 1
- 资源: 1
上传资源 快速赚钱
我的内容管理
展开
- 我的资源
快来上传第一个资源
我的收益 登录查看自己的收益
我的积分
登录查看自己的积分
我的C币
登录后查看C币余额
我的收藏 
我的下载 
下载帮助
前往需求广场，查看用户热搜
安全验证
文档复制为VIP权益，开通VIP直接复制
信息提交成功